ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 27

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers
Indexed Control Register Set
OXFORD SEMICONDUCTOR LTD.
Register
Name
MDM
NMR
DMS
PIDX
MDR
ACR
CPR
TCR
CKS
FCH
REV
CSR
RFC
GDS
CKA
TTL
RTL
FCL
ID1
ID2
ID3
via ICR. Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Control Registers use the following procedure.
Offset
SPR
0x0C
0x0D
0X0F
0X10
0xFE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x11
0x12
0x13
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
Unused
Unused
Unused
Unused
internal
inactive
Enable
FCR[7]
TxRdy
Status
Bit 7
Addit-
Tx 1x
Mode
Force
ional
Unused
Table 24: Indexed Control Register Set
Unused
Tx CLK
internal
inactive
Enable
FCR[6]
RxRdy
Select
Bit 6
Read
Force
ICR
Unused
Unused
5 Bit “integer” part of
clock prescaler
reset the UART (Except the CKS and CKA registers)
SChar 4
BDOUT
on DTR
Trigger
Enable
FCR[5]
Bit 5
9
Level
950
th
Automatic Flow Control Lower Trigger Level (0-127)
Automatic Flow Control Higher Trigger level (1-127)
Bit
Writing 0x00 to this register will
Hardwired revision byte (0x06)
Hardwired Port Index ( 0x00 )
Transmitter Interrupt Trigger Level (0-127)
Hardwired ID byte 1 (0xC9)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0x50)
Receiver Interrupt Trigger Level (1-127)
Schar 3
Unused
Write ‘0’
Unused
DTR 1x
Tx CLK
FCR[4]
Bit 4
DTR definition and
9
Res.
th
Bit
Unused
control
SChar 2
Wakeup
Write ‘0’
disable
FCR[3]
Bit 3
9
Rx 1x
Mode
Res.
th
DCD
OXCF950 DATA SHEET V1.1
Bit
SChar 1
RI edge
Control
BDOUT
Trailing
Enable
Disable
disable
FCR[2]
Bit 2
4 Bit N-times clock
signal
9
Invert
selection bits [3:0]
Auto
DSR
Flow
DTR
th
Bit
3 Bit “fractional” part of
clock prescaler
9
Wakeup
Disable
disable
FCR[1]
Internal
internal
tx clock
th
TxRdy
Bit 1
status
Invert
-bit Int.
( R )
En.
Tx
DSR
Clock Sel[1:0]
Receiver
Wakeup
Disable
Internal
internal
rx clock
Page 27
Enable
disable
FCR[0]
enable
RxRdy
Status
Bit 0
Good
status
Invert
Local
Data
9 Bit
( R )
Bus
Rx
CTS