gs840e32agt-180i GSI Technology, gs840e32agt-180i Datasheet - Page 15
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gs840e32agt-180i
Manufacturer Part Number
gs840e32agt-180i
Description
256k X 18, 128k X 32, 128k X 36 4mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
1.GS840E32AGT-180I.pdf
(32 pages)
- Current page: 15 of 32
- Download datasheet (951Kb)
Notes:
1.
2.
3.
Rev: 1.14 10/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
X
X
CW
First Write
Burst Write
W
Simplified State Diagram with G
W
CW
15/32
W
CR
R
CR
R
Deselect
X
CW
W
CW
W
R
GS840E18/32/36AT/B-180/166/150/100
CR
First Read
Burst Read
R
R
CR
X
X
© 1999, GSI Technology
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