ak4589 AKM Semiconductor, Inc., ak4589 Datasheet - Page 43

• Manufacturer Part Number: ak4589
• Description: 2/8-channel Audio Codec With Dir
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The AK4589 has a Non-PCM steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit “1”. Once the AUTO bit is
set “1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers. The
AK4589 also has the DTS-CD bitstream auto-detection function. When The AK4589 detects DTS-CD bitstreams,
DTSCD bit goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until when
AK4589 detects the stream again.
On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4589
has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel
status, AK4589 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz). The
PLL loses lock when the received sync interval is incorrect.
The AK4589 has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 17. The 512fs clock will not output when 96kHz and 192kHz. The 256fs clock will not output
when 192kHz.
The CM0/CM1 pins (or bits) select the clock source and the data source of SDTO. In Mode 2, the clock source is
switched from PLL to X'tal when PLL goes unlock state. In Mode3, the clock source is fixed to X'tal, but PLL is also
operating and the recovered data such as C bits can be monitored. For Mode2 and 3, it is recommended that the
frequency of X’tal is different from the recovered frequency from PLL.
MS0339-E-00
Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
192kHz Clock Recovery
Master Clock
Clock Operation Mode
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Mode
No.
0
1
2
3
0
1
2
3
OCKS1
CM1
0
0
1
1
0
0
1
1
CM0
OCKS0
0
1
0
1
Table 17. Master Clock Frequency Select (Stereo mode)
0
1
0
1
ON: Oscillation (Power-up), OFF: STOP (Power-down)
OPERATION OVERVIEW (DIR/DIT part)
UNLOCK
Table 18. Clock Operation Mode select
MCKO1
0
1
-
-
-
128fs
256fs
256fs
512fs
OFF
PLL
ON
ON
ON
ON
MCKO2
256fs
128fs
256fs
- 43 -
64fs
ON(Note)
X'tal
ON
ON
ON
ON
256fs
256fs
512fs
128fs
X’tal
Clock source
X'tal
X'tal
X'tal
PLL
PLL
192 kHz
fs (max)
96 kHz
96 kHz
48 kHz
SDTO
RX
DAUX
RX
DAUX
DAUX
Default
Default
[AK4589]
2004/09