ak4589 AKM Semiconductor, Inc., ak4589 Datasheet - Page 68

• Manufacturer Part Number: ak4589
• Description: 2/8-channel Audio Codec With Dir
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
(2) I
AK4589 supports the standard-mode I
system (max: 400kHz).
(2)-1 Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4589 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
(2)-1-1 Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
(2)-1-2 START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
MS0339-E-00
2
C bus control mode (I2C pin = “H”)
SCL
SDA
SCL
SDA
START CONDITION
Figure 42. START and STOP conditions
2
C-bus (max: 100kHz). Then AK4589 does not support a fast-mode I
DATA VALID
DATA LINE
STABLE :
Figure 41. Data transfer
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CHANGE
OF DATA
ALLOWED
STOP CONDITION
[AK4589]
2004/09
2
C-bus