ak4642e AKM Semiconductor, Inc., ak4642e Datasheet
ak4642e
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ak4642e Summary of contents
Page 1
... External Clock Mode • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0420-E-00 Stereo CODEC with MIC/HP/SPK-AMP GENERAL DESCRIPTION FEATURES S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) 3.0Vrms@50Ω (HVDD=5V [AK4642EN] AK4642EN 2005/09 ...
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... MIC-Amp A/D HPF Reduction Separation PMADR PMLO PMHPL PMDAC DATT Bass D/A ALC SMUTE Boost PMSPK PMBP MIN HVSS Figure 1. Block Diagram - 2 - [AK4642EN DVDD DVSS I2C CSN Cont rol Register CCLK CDTI PDN Stereo ALC BICK LRCK SDTO SDTI Audio I/F Stereo HPF ...
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... Evaluation board for AK4642 Pin Layout MUTET 25 ROUT 26 LOUT 27 MIN 28 RIN2 / IN2− 29 LIN2 / IN2+ 30 LIN1 / IN1− 31 RIN1 / IN1+ 32 MS0420-E-00 32pin QFN (0.5mm pitch AK4642EN 13 Top View [AK4642EN] DVSS DVDD BICK LRCK SDTO SDTI CDTI / SDA CCLK / SCL 2005/09 ...
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... C(100kHz mode) Available Available Available Available Available Available 2.4 ∼ 3.6V 52pin QFN (7.2mm x 7.2mm [AK4642EN] AK4642EN Single-ended / Full-differential 2-Input selectable 1-Output, R =0.5kΩ (min) L +32dB/+26dB/+20dB or 0dB +36dB to –54dB, 0.375dB step, Mute Available Available Available Line/HP/SP, +36dB to –54dB +12 to –115dB, Mute +5 ...
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... N/A N/A SP only, +18dB to –8dB N/A N/A N/A Mono N/A Mono 1.98Vpp 3-wire Available Available Available 28pin QFN (5.2mm x 5.2mm [AK4642EN] AK4642EN Single-ended / Full-differential Available Stereo +36dB to –54dB, 0.375dB step, Mute Available Available Line/HP/SP, +36dB to –54dB Available Available Available Stereo Available Stereo 1.98Vpp/2.50Vpp 2 3-wire/I C ...
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... ALC ZELMN REF6 REF5 REF4 IVL6 IVL5 IVL4 DVL6 DVL5 DVL4 LMTH1 0 0 Additional Function for AK4642 only Bits which are not needed for AK4642 - 6 - [AK4642EN PMAO PMDAC PMMIC PMADC M/S MCKPD MCKO PMPLL DACM MPWR MICAD MGAIN0 SPKG0 BEEPA ...
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... Function 2 C Bus, “L”: 3-wire Serial (MDIF2 bit = “0”) (MDIF2 bit = “1”) (MDIF2 bit = “0”) (MDIF2 bit = “1”) (MDIF1 bit = “0”) (MDIF1 bit = “1”) (MDIF1 bit = “0”) (MDIF1 bit = “1” [AK4642EN] 2005/09 ...
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... The unused I/O pins should be processed appropriately as below. Classification Pin Name MPWR, VCOC, SPN, SPP, HPR, HPL, MUTET, Analog ROUT, LOUT, MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ MCKO Digital MCKI MS0420-E-00 Setting These pins should be open. This pin should be open. This pin should be connected to DVSS [AK4642EN] 2005/09 ...
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... AVDD −0.3 DVDD −0.3 HVDD ∆GND1 (Note 4) ∆GND2 (Note 4) IIN −0.3 VINA −0.3 VIND −30 Ta −65 Tstg Pd1 Pd2 Symbol min AVDD 2.6 DVDD 2.6 HVDD 2.6 −0.3 AVDD−DVDD - 9 - [AK4642EN] max Units 6.0 V 6 0.3 V ± AVDD+0.3 V DVDD+0.3 V °C 85 °C 150 - 400 mW - 550 mW ...
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... Units 60 80 kΩ kΩ + + + 0.228 Vpp - 0.114 Vpp - 0.057 Vpp 2. kΩ ...
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... L =100Ω (Note 19) 80 (Note 20) - (Note 19) 65 (Note 20) - (Note 19) - (Note 20 =22.8Ω. L =100Ω. L HPL/HPR pin Measurement Point 47µF 6.8Ω 0.22µF C1 10Ω Figure 2. Headphone-Amp output circuit - 11 - [AK4642EN] typ max Units - 16 Bits 1.98 2.18 Vpp 2.50 2.75 Vpp 88 - dBFS 100 - dB 0.1 0 kΩ 1.98 2.38 Vpp 3 ...
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... Units =8Ω, BTL Vpp 4.71 Vpp - Vrms - Ω =3µF, R =10Ω serial - Vpp 10.20 Vpp - Ω - µ Vpp +4 −15 +8. ...
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... Note 28. PMADL = PMADR = PMDAC = PMLO = PMSPK = PMVCM = PMPLL = PMBP bits = “1” and PMHPL = PMHPR bits = “0”. Note 29. All digital input pins are fixed to DVDD or DVSS. MS0420-E-00 min typ - [AK4642EN] max Units µA 100 2005/09 ...
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... Note 33. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0420-E-00 FILTER CHARACTERISTICS Symbol min 26 ∆ 25 [AK4642EN] typ max Units - 17.3 kHz 19.4 - kHz 19.9 - kHz 22.1 - kHz - - kHz ±0 1/fs µ 19.6 kHz 20.0 - kHz 22.05 - kHz - - kHz ±0. ...
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... Duty - tBCK - tBCK - dBCK - fCLK 11.2896 tCLKL 0.4/fCLK tCLKH 0.4/fCLK fMCK 0.2352 dMCK 40 dMCK - fs 7.35 Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 15 - [AK4642EN] typ Max Units - - V - 30%DVDD 0 0.4 V ±10 µA - typ max Units - 27 MHz - - 12.288 MHz 50 60 ...
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... Units 48 kHz 55 % 1/(32fs kHz 12.288 MHz 13.312 MHz 13.312 MHz - kHz 26 kHz 13 kHz 55 ...
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... Units - - 400 kHz µ µ µ µ µ µs ...
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... Figure 4. Audio Interface Timing (PLL Master mode) MS0420-E-00 1/fCLK tCLKL 1/fs tLRCKH tLRCKL Duty = tLRCKH 100 tLRCKL 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 tBCKL tDLR tSDS tSDH - 18 - [AK4642EN] VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD tBSD 50%DVDD VIH VIL 2005/09 ...
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... Duty = tLRCKH 100 tLRCKH tLRCKL tBCK tBCKH tBCKL Figure 6. Clock Timing (EXT Slave mode [AK4642EN] VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL tLRCKL 100 VIH VIL ...
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... ASAHI KASEI LRCK tBLR BICK tLRD SDTO SDTI Figure 7. Audio Interface Timing (PLL/EXT Slave mode) MS0420-E-00 tLRB tBSD MSB tSDS tSDH - 20 - [AK4642EN] VIH VIL VIH VIL 50%DVDD VIH VIL 2005/09 ...
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... C1 C0 Figure 8. WRITE Command Input Timing tCSH D1 D0 Figure 9. WRITE Data Input Timing tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 10 Bus Mode Timing - 21 - [AK4642EN] VIH VIL VIH VIL tCCK tCDH VIH R/W VIL tCSW VIH VIL VIH VIL VIH VIL VIH ...
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... ASAHI KASEI PMADL bit or PMADR bit SDTO PDN MS0420-E-00 tPDV Figure 11. Power Down & Reset Timing 1 tPD Figure 12. Power Down & Reset Timing [AK4642EN] 50%DVDD VIL 2005/09 ...
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... Selected by 0 “L” FS3-0 bits Table 2. Clock pins state in Clock Mode M/S bit Mode 0 Slave Mode Default 1 Master Mode - 23 - [AK4642EN] PLL3-0 bits Figure See Table 4 Figure 13 See Table 4 Figure 14 See Table 4 Figure 15 x Figure BICK pin LRCK pin ...
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... Others - 24 - [AK4642EN] R and C of PLL Lock VCOC pin Time C[F] R[Ω] (max) 6.8k 220n 160ms Default - - - 10k 4.7n 2ms ...
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... Output See Table 9 MCKO pin MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 25 - [AK4642EN] BICK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 10 1fs Output “1”. ...
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... DSP or µP 256fs/128fs/64fs/32fs MCLK 32fs, 64fs BCLK 1fs LRCK SDTI SDTO Figure 13. PLL Master Mode PS1 bit PS0 bit MCKO pin 0 0 256fs 0 1 128fs 1 0 64fs 1 1 32fs BICK Output Frequency 0 32fs Default 1 64fs - 26 - [AK4642EN] Default 2005/09 ...
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... ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). MS0420-E-00 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or µP 256fs/128fs/64fs/32fs MCLK ≥ 32fs BCLK 1fs LRCK SDTI SDTO DSP or µP MCKO MCKI 32fs, 64fs BCLK BICK 1fs LRCK LRCK SDTI SDTO SDTO SDTI - 27 - [AK4642EN] 2005/09 ...
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... DSP or µP MCKO 256fs, 512fs or 1024fs MCKI MCLK ≥ 32fs BCLK BICK 1fs LRCK LRCK SDTI SDTO SDTO SDTI Figure 16. EXT Slave Mode - 28 - [AK4642EN] Sampling Frequency Range 7.35kHz ∼ 48kHz Default 7.35kHz ∼ 13kHz 7.35kHz ∼ 48kHz 7.35kHz ∼ 26kHz N/A 2005/09 ...
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... Don't Care Lch Data Figure 17. Mode 1 Timing - 29 - [AK4642EN] BICK Figure N/A - ≥ 32fs Figure 17 ≥ 32fs Figure 18 Default ≥ 32fs Figure ...
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... Lch Data Figure 19. Mode 3 Timing ADC Lch data 0 All “0” 1 Rch Input Signal 0 Lch Input Signal 1 Lch Input Signal Table 14. Mono/Stereo ADC operation - 30 - [AK4642EN ...
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... LIN1 1 x N IN1+/− IN1+/− Table 15. MIC/Line In Path Select INL bit MDIF1 bit INR bit MDIF2 bit Figure 20. Mic/Line Input Selector - 31 - [AK4642EN] Rch RIN1 Default RIN2 RIN1 RIN2 IN2+/− N/A N/A RIN2 IN2+/− ADC Lch ADC Rch 2005/09 ...
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... MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 16. Mic Input Gain PMMP bit MPWR pin 0 Hi-Z Default 1 Output Table 17. MIC Power MPWR pin LIN1 pin RIN1 pin LIN2 pin RIN2 pin Figure 22. MIC Block Circuit - 32 - [AK4642EN] Default Microphone Microphone Microphone Microphone 2005/09 ...
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... An y coefficient EQA15-0 MUTE EQB13-0 (set by EQC15-0 FIL3 coefficient) +12dB ∼ 0dB Figure 23. Digital EQ/HPF/LPF GN0 Gain 0 0dB 1 +12dB x +24dB - 33 - [AK4642EN] st Digital EQ/HPF/LPF Power-down Default Playback path Recording path Recording path Recording path Gain ALC GN1-0 +24/+12/0dB Default 2005/09 ...
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... Amplitude 2 − 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs [AK4642EN] Phase (B+1)sin (2πf/fs) − (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) − (B+1)cos (2πf/fs) 2005/09 ...
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... /fs tan (πfc /fs Amplitude 2ACcos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) =3000Hz, Gain=+8dB 2 fc Frequency [AK4642EN] 1 − tan (πfc /fs) 2 K/ tan (πfc /fs) 1 Phase (AB−C)sin (2πf/fs) − (AB+C)cos (2πf/fs) 13 2005/09 ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms - 36 - [AK4642EN] ALC Power-down Default Playback path Recording path Recording path Recording path Default 0.375dB Default 0.750dB 1.500dB 3.000dB 0.375dB 44.1kHz 2.9ms Default 5 ...
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... RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 25. ALC Recovery GAIN Step GAIN(dB) Step +36.0 +35.625 +35.25 : +30.375 +30.0 0.375dB +29.625 : −53.25 −53.625 −54.0 MUTE - 37 - [AK4642EN] 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms Default Default 2005/09 ...
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... Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” * The value of IVOL should be the same or smaller than REF’ [AK4642EN] fs=44.1kHz Data Operation −4.1dBFS 01 0 Enable 11 23 ...
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... Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H MS0420-E-00 GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 +30.0 0.375dB +29.625 : −53.25 −53.625 −54 MUTE Table 28. Input Digital Volume Setting - 39 - [AK4642EN] Default 2005/09 ...
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... When ALC is enabled again, ALC bit should be set to “1” interval more than zero crossing timeout period after ALC bit = “0”. MS0420-E-00 Enable E1H(+30dB) C6H(+20dB) E1(+30dB) --> F1(+36dB) E1(+30dB) (1) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB [AK4642EN] Disable 2005/09 ...
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... Figure 26. Bass Boost Frequency Response (fs=44.1kHz) BST1 MS0420-E-00 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 29. De-emphasis Control Boost Filter (fs=44.1kHz) 100 1000 Frequency [Hz] BST0 Mode 0 OFF Default 1 MIN 0 MID 1 MAX Table 30. Bass Boost Control - 41 - [AK4642EN] 10000 2005/09 ...
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... Table 32. Transition Time Setting of Digital Output Volume MS0420-E-00 DVL/R7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB : : 18H 0dB : : −114.5dB FDH −115.0dB FEH FFH MUTE (−∞) Table 31. Digital Volume Code Table Setting fs=8kHz 1061/fs 133ms 256/fs 32ms - 42 - [AK4642EN] Default fs=44.1kHz 24ms Default 6ms 2005/09 ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0420-E- bit ( (2) Figure 27. Soft Mute Function - 43 - [AK4642EN] ( 2005/09 ...
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... Headphone-Amp Output Gain (typ MIN SPP/SPN ALC bit = “0” ALC bit = “1” +4.43dB +6.43dB +6.43dB +8.43dB +10.65dB +12.65dB +12.65dB +14.65dB Speaker-Amp Output Gain (typ [AK4642EN] LOUT/ROUT pin HPL/HPR pin SPP/SPN pin Default = 20kΩ i Default = 20kΩ i Default = 20kΩ i 2005/09 ...
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... LOUT/ROUT pin Power-down Pull-down to AVSS Normal Operation Normal Operation Power-save Fall down to AVSS Power-save Rise up to VCOM Gain Output Voltage (typ) 0dB 0.6 x AVDD Default +2dB 0.757 x AVDD LOUT 1µF 220Ω ROUT - 45 - [AK4642EN] LOUT pin ROUT pin Default 20kΩ 2005/09 ...
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... LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1µF. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0420-E- [AK4642EN ≥ 2005/09 ...
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... Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0420-E-00 0 0.6 x AVDD Table 38. Headphone-Amp Output Voltage (3) ( [AK4642EN] 1 0.91 x AVDD “0”: 500ms(max) 2005/09 ...
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... MS0420-E- Headphone 16Ω 0.22µ 10Ω fc [Hz] fc [Hz] BOOST=OFF BOOST=MIN @fs=44.1kHz 70 28 149 106 100 137 69 Table 39. External Circuit Example - 48 - [AK4642EN] is 16Ω. Output powers are shown at L Output Power [mW]@0dBFS 2.7V 3.0V 3.3V 10.1 12.5 15.1 5.1 6.3 7 0.9 1.1 1.3 2005/09 ...
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... Table 42. SPK-Amp Output Level - 49 - [AK4642EN] 2.6 ∼ 5.25V 50Ω (Note 23) 3µF (Note 23) Default ALC bit = “1” (LMTH1-0 bits = “00”) 3.11Vpp 3.92Vpp 6.37Vpp (Note 40) 8.02Vpp (Note 40) 3.11Vpp 3.92Vpp 6.37Vpp 8.02Vpp ...
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... For example, zener diode which zener voltage is 5.1V(Min: 4.97V, Max: 5.24V) can be used. SPK-Amp Figure 33. Speaker Output Circuit (Load Capacitance > 30pF) MS0420-E-00 fs=44.1kHz Data Operation −2.5dBFS 00 0 Enable 10 11.6ms 11 23.2ms C1H +18dB 91H 0dB 00 1 step 00 1 step 1 Enable ZD ≥10Ω SPP SPN ≥10Ω [AK4642EN] 2005/09 ...
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... Table 44. Speaker-Amp Mode Setting (x: Don’t care) PMSPK bit SPPSN bit SPP pin Hi-Z HVDD/2 SPN pin Hi-Z Figure 34. Power-up/Power-down Timing for Speaker-Amp MS0420-E-00 Mode SPP Power-down Hi-Z Power-save Hi-Z Normal Operation Normal Operation - 51 - [AK4642EN] SPN Hi-Z Default HVDD/2 Normal Operation Hi-Z HVDD/2 Hi-Z 2005/09 ...
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... R/W “1” Chip Address (C1 = “1” “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 35. Serial Control I/F Timing - 52 - [AK4642EN] 2005/09 ...
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... C-bus mode. All commands are preceded by a START condition. A Data(n) Data(n+ C-Bus Mode Figure 37. The First Byte Figure 38. The Second Byte [AK4642EN Data(n+ CAD0 R 2005/09 ...
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... Data(n+1) Data(n+ Figure 40. CURRENT ADDRESS READ R/W="1" Slave S Data(n) Data(n+1) Address Figure 41. RANDOM ADDRESS READ - 54 - [AK4642EN Data(n+ Data(n+ ...
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... MASTER S START CONDITION SDA SCL MS0420-E-00 Figure 42. START and STOP Conditions Figure 43. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 44. Bit Transfer on the I C-Bus - 55 - [AK4642EN] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2005/09 ...
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... EQB6 EQB5 EQB4 0 0 EQB13 EQB12 EQC6 EQC5 EQC4 EQC14 EQC13 EQC12 F1A6 F1A5 F1A4 0 F1A13 F1A12 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 - 56 - [AK4642EN PMLO PMDAC 0 PMADL M/S 0 MCKO PMPLL 0 PMMP 0 MGAIN0 SPKG0 BEEPL 0 0 BCKO 0 DIF1 DIF0 0 FS2 FS1 ...
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... The register values remain unchanged. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0420-E- PMVCM PMBP PMSPK PMLO [AK4642EN PMDAC 0 PMADL 2005/09 ...
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... Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (Default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (Default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (Default) 1: Normal operation MS0420-E- HPMTN PMHPL PMHPR M [AK4642EN MCKO PMPLL 2005/09 ...
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... HVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “H”, Speaker-Amp is in power-down mode since PMSPK bit is “0”. MS0420-E- BEEPS DACS DACL [AK4642EN PMMP 0 MGAIN0 2005/09 ...
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... LOPS SPKG1 MGAIN1 PLL3 PLL2 PLL1 PLL0 PS1 PS0 FS3 [AK4642EN SPKG0 BEEPL BCKO 0 DIF1 DIF0 FS2 FS1 FS0 ...
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... D4 0 ZTM1 ZTM0 ALC ZELMN REF6 REF5 REF4 [AK4642EN WTM1 WTM0 LMAT1 LMAT0 LMTH0 RGAIN0 REF3 REF2 REF1 REF0 ...
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... DVR6 DVR5 DVR4 LMTH1 LOOP SMUTE DVOLC [AK4642EN IVL3 IVL2 IVL1 IVL0 IVR3 IVR2 IVR1 IVR0 DVL3 DVL2 DVL1 DVL0 DVR3 DVR2 DVR1 DVR0 1 0 ...
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... When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. MS0420-E- [AK4642EN IVOLC HPM BEEPH DACH 2005/09 ...
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... MDIF2: ADC Rch Input Type Select 0: Single-ended input (RIN1/RIN2 pin: Default) 1: Full-differential input (IN2+/IN2− pin) HPG: Headphone-Amp Gain Select (see Table 38.) 0: 0dB (Default) 1: +3.6dB MS0420-E- HPG MDIF2 MDIF1 [AK4642EN INR INL PMADR 2005/09 ...
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... Disable (Default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). MS0420-E- GN1 GN0 0 FIL1 [AK4642EN FIL3 2005/09 ...
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... EQC14 EQC13 EQC12 F1A7 F1A6 F1A5 F1A4 F1AS 0 F1A13 F1A12 F1B7 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 [AK4642EN F3A3 F3A2 F3A1 F3A0 F3A11 F3A10 F3A9 F3A8 F3B3 F3B2 F3B1 F3B0 F3B11 F3B10 F3B9 F3B8 EQA3 EQA2 EQA1 ...
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... ZD1 10 0.22u 10 0.22u 25 MUTET ROUT 26 LOUT 27 AK4642EN MIN 28 RIN2 Top View 29 LIN2 30 31 LIN1 32 RIN1 [AK4642EN] R1, R2: Short ZD1, ZD2: Open R1, R2: ≥10Ω ZD1, ZD2: Required 0.1u DVSS 16 DVDD 15 BICK 14 DSP LRCK 13 SDTO 12 SDTI 11 CDTI 10 CCLK 9 µP Digital Ground Analog Ground ...
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... ZD1 10 0.22u 10 0.22u 25 MUTET ROUT 26 LOUT 27 AK4642EN MIN 28 RIN2 Top View 29 LIN2 30 31 LIN1 32 RIN1 [AK4642EN] R1, R2: Short ZD1, ZD2: Open R1, R2: ≥10Ω ZD1, ZD2: Required 0.1u DVSS 16 DVDD 15 BICK 14 DSP LRCK 13 SDTO 12 SDTI 11 CDTI 10 CCLK 9 µP Digital Ground Analog Ground ...
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... The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2. MS0420-E- [AK4642EN] 2005/09 ...
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... Sampling Frequency: 8kHz (1) Power Supply & PDN pin = “L” Input 40msec(max) (6) Output 40msec(max) (8) Output (7) Figure 47. Clock Set Up Sequence (1) “H” “1” [AK4642EN] “H” (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:00H (3)Addr:00H, Data:40H (4)Addr:01H, Data:0BH MCKO, BICK and LRCK output 2005/09 ...
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... Power Supply & PDN pin = “L” Input (4) (5) Figure 48. Clock Set Up Sequence (2) “H” “1” [AK4642EN] PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz “H” (2) Addr:04H, Data:32H Addr:05H, Data:00H (3) Addr:00H, Data:40H (4) Addr:01H, Data:01H 2005/09 ...
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... Sampling Frequency: 8kHz (1) Power Supply & PDN pin = “L” Input 40msec(max) (6) Output (7) (8) Input Figure 49. Clock Set Up Sequence (3) “H” “1” [AK4642EN] “H” (2)Addr:04H, Data:4AH Addr:05H, Data:00H (3)Addr:00H, Data:40H (4)Addr:01H, Data:03H MCKO output start BICK and LRCK input start 2005/09 ...
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... Input MCKI frequency: 1024fs Sampling Frequency: 8kHz MCKO: Disable (1) Power Supply & PDN pin = “L” Input Input MCKI, BICK and LRCK input Figure 50. Clock Set Up Sequence (4) “H” “1” [AK4642EN] “H” (2) Addr:04H, Data:02H Addr:05H, Data:01H (3) Addr:00H, Data:40H 2005/09 ...
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... ALC Enable ALC Disable 1059 / fs (8) (7) Initialize Normal State Power Down Figure 51. MIC Input Recording Sequence - 74 - [AK4642EN] Example: PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Figrure 23 ALC bit=“1” ...
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... HVDD/2 Hi-Z Figure 52. Speaker-Amp Output Sequence “1” “01” SPK-Amp”: DACS bit = “1” “0” [AK4642EN] Example: PLL Master Mode Audio I/F Format: MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: 0dB ALC: Enable (1) Addr:05H, Data:27H (2) Addr:02H, Data:20H ...
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... Hi-Z Speaker-Amp” Output Sequence SPK-Amp”: DACS bit = “0” SPK-Amp”: BEEPS bit = “0” → “1” SPK-Amp”: BEEPS bit = “1” → “0” [AK4642EN] Example: (1) Addr:00H, Data:70H (2) Addr:02H, Data:60H (3) Addr:02H, Data:E0H Mono Signal Output (4) Addr:02H, Data:60H ...
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... GND [AK4642EN lin “ 1 ” ita ...
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... Stereo Line Amp”: DACL bit = “0” “1” “0” “1” Stereo Line-Amp”: DACL bit = “1” “0” [AK4642EN] Example: PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: 0dB MGAIN1=SPKG1=SPKG0=BEEPL bits = “0” ...
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... Addr:01H, Data:08H (3) Stop an external MCKI Figure 56. Clock Stopping Sequence (1) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz Figure 57. Clock Stopping Sequence ( [AK4642EN] (1) Addr:01H, Data:00H (2) Stop the external clocks 2005/09 ...
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... PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz Figure 58. Clock Stopping Sequence (3) Example Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz Figure 59. Clock Stopping Sequence ( [AK4642EN] (1) Addr:01H, Data:00H (2) Stop the external clocks (1) Stop the external clocks 2005/09 ...
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... Note) The exposed pad on the bottom surface of the package must be open or connected to the grournd. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0420-E-00 PACKAGE 0.40 ± 0. C0. Epoxy Cu Solder (Pb free) plate - 81 - [AK4642EN] Exposed Pad 32 1 3.5 2005/09 ...
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... ASAHI KASEI Date (YY/MM/DD) Revision Reason 05/09/15 00 First Edition MS0420-E-00 MARKING AKM AK4642 XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Page Contents - 82 - [AK4642EN] 2005/09 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0420-E-00 IMPORTANT NOTICE - 83 - [AK4642EN] 2005/09 ...