ak4642e AKM Semiconductor, Inc., ak4642e Datasheet - Page 75

• Manufacturer Part Number: ak4642e
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0420-E-00
Speaker-amp Output
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Speaker-Amp should be
(2) Set up the path of “DAC
(3) SPK-Amp gain setting: SPKG1-0 bits = “00”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(8) Set up the input digital volume (Addr: 09H and 0CH)
(9) Set up the output digital volume (Addr: 0AH and 0DH).
(10) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “0” → “1”
(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(13) Disable the path of “DAC
(14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “1” → “0”
powered-up in consideration of PLL lock time after a sampling frequency is changed.
When PMADL or PMADR bit is “1”, ALC for DAC path is disabled.
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is
“1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
(Addr:05H, D5&D2-0)
(Addr:09H&0CH, D7-0)
(Addr:0AH&0DH, D7-0)
SPKG1-0 bits
(Addr:03H, D4-3)
(Addr:02H, D3)
ALC Control 1
(Addr:07H, D5)
(Addr:00H, D2)
(Addr:00H, D5)
(Addr:00H, D4)
(Addr:02H, D7)
PMDAC bit
ALC Control 2
ALC Control 3
DVL/R7-0 bits
PMSPK bit
SPPSN bit
DACS bit
IVL/R7-0 bits
PMBP bit
FS3-0 bits
SPN pin
SPP pin
ALC bit
(Addr:06H)
(Addr:0BH)
(Addr:08H)
X,XXX
00
XXH
XXH
XXH
E1H
18H
0
(2)
SPK-Amp”: DACS bit = “0”
(1)
(3)
Hi-Z
Figure 52. Speaker-Amp Output Sequence
(4)
(5)
SPK-Amp”: DACS bit = “1”
Hi-Z
(6)
(7)
(8)
(9)
(10)
HVDD/2
(11)
1,111
01
3CH
C1H
00H
X
Normal Output
Normal Output
91H
XXH
- 75 -
“01”
(12)
HVDD/2
(13)
Hi-Z
“1”
(14)
Hi-Z
“0”
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
ALC: Enable
(1) Addr:05H, Data:27H
(4) Addr:06H, Data:3CH
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:08H
(5) Addr:08H, Data:E1H
(6) Addr:0BH, Data:00H
(7) Addr:07H, Data:20H
(8) Addr:09H & 0CH, Data:91H
(9) Addr:0AH & 0DH, Data:28H
(10) Addr:00H, Data:74H
(11) Addr:02H, Data:A0H
(12) Addr:02H, Data:20H
(13) Addr:02H, Data:00H
(14) Addr:00H, Data:40H
Playback
[AK4642EN]
2005/09