ak4642e AKM Semiconductor, Inc., ak4642e Datasheet - Page 79

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ak4642e

Manufacturer Part Number
ak4642e
Description
Stereo Codec With Mic/hp/spk-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
Master clock can be stopped when ADC and DAC are not used.
MS0420-E-00
External LRCK
External MCKI
External BICK
1. PLL Master Mode
2. PLL Slave Mode (LRCK or BICK pin)
Stop of Clock
(Addr:01H, D0)
(Addr:01H, D1)
(Addr:01H, D0)
<Example>
<Example>
PMPLL bit
PMPLL bit
MCKO bit
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
"H" or "L"
Input
Input
Input
(1)
(1)
(2)
(3)
(2)
(2)
Figure 56. Clock Stopping Sequence (1)
Figure 57. Clock Stopping Sequence (2)
- 79 -
Example:
Example
Input Master Clock Select at PLL Mode: 11.2896MHz
BICK frequency at Master Mode: 64fs
Audio I/F Format : MSB justified (ADC & DAC)
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 8kHz
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
(2) Stop the external clocks
(1) Addr:01H, Data:00H
[AK4642EN]
2005/09

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