ak4642e AKM Semiconductor, Inc., ak4642e Datasheet - Page 78

• Manufacturer Part Number: ak4642e
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0420-E-00
(Addr:05H, D5&D2-0)
(Addr:0AH&0DH, D7-0)
(Addr:09H&0CH, D7-0)
Stereo Line Output
(Addr:02H, D4)
(Addr:03H, D6)
(Addr:00H, D2)
(Addr:00H, D5)
(Addr:00H, D3)
<Example>
PMDAC bit
DVL/R7-0 bits
ROUT pin
IVL/R7-0 bits
DACL bit
PMLO bit
LOUT pin
LOPS bit
PMBP bit
FS3-0 bits
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Stereo Line-Amp
(2) Set up the path of “DAC
(3) Set up the input digital volume (Addr: 09H and 0CH)
(4) Set up the output digital volume (Addr: 0AH and 0DH)
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0” → “1”
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1” → “0”
(10) Disable the path of “DAC
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max)
at C=1µF.
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1µF.
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
X,XXX
E1H
18H
(1)
(2)
(4)
(3)
(5)
Stereo Line Amp”: DACL bit = “0”
(6)
>300 ms
Stereo Line-Amp”: DACL bit = “1”
Figure 55. Stereo Lineout Sequence
(7)
1,111
XXH
Normal Output
91H
- 78 -
(8)
(9)
(10)
>300 ms
“1”
“0”
“0”
“1”
(11)
“1”
“0”
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”
(6) Addr:00H, Data:6CH
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
(5) Addr:03H, Data:40H
(7) Addr:03H, Data:00H
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
(3) Addr:09H&0CH, Data:91H
(4) Addr:0AH&0DH, Data:28H
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
Playback
[AK4642EN]
2005/09