m21353 Mindspeed Technologies, m21353 Datasheet - Page 25

• Manufacturer Part Number: m21353
• Description: 4.25 Gbps Twelve-channel Backplane Equalizer And Driver With 12x12 Crosspoint Switch
• Manufacturer: Mindspeed Technologies

5.1
The M21353 includes four distinct power supply domains: AVDDCORE, DVDDCORE, AVDDIO, and DVDDIO.
AVDDCORE powers the analog core circuitry in the device, and must be set to 1.2V.
DVDDCORE powers the digital core circuitry in the device, and must be set to 1.2V.
AVDDIO powers the input/output circuits in the device, and can be set to either 1.2V or 1.8V. Note that to achieve
output swing levels higher than 800 mVppd, AVDDIO must be set to 1.8V.
DVDDIO powers the digital circuitry within the device, and can be set to 1.2V, 1.8V, 2.5V, or 3.3V to allow for
interface with various external digital devices. It is recommended that DVDDIO is connected to the same voltage
level as any digital devices that are used to control the M21353.
5.2
The input buffers in the M21353 are designed to work with AC coupled input signals, and support operation with a
wide range of AC coupling capacitor values. Applications that use PRBS and/or 8b/10b encoded data will typically
use AC coupling capacitors with a value of 0.1 uF. SDI video applications will typically use AC coupling capacitors
with a value of 4.7 uF or larger. The output buffers are designed with PCML logic, and can operate with either AC
coupled or DC coupled systems. To enable support for the PCIe receiver detect function, the input buffer can be
configured in a high-impedance state where the single ended input impedance is greater than 100 kΩ. The input
buffer should not be configured in a high-impedance state when data needs to be passed through the M21353. For
typical operation, the input buffer should be enabled with a 50Ω single ended (100Ω differential) termination. The
high-speed outputs are powered-down by default, and should be set to the desired output swing level using
registers 41h-4Ch.
5.3
There is signal detect circuit that will assert an alarm if the signal level at the input of the device is lower than the
assert threshold level of the LOS circuit of the squelch is forced on for an input. Once asserted, the alarm will
remain asserted until the signal is above the de-assert threshold level of the LOS circuit or the force squelch on an
input channel has been removed. There is hysteresis between the assert and de-assert levels to prevent chattering
of the LOS alarm. Please refer to
LOS circuit should be disabled when used with strings of 1010 data that last for more than approximately 3 μs to
avoid false LOS alarms. The LOS alarm status register (address C3h, C4h), will latch when the LOS alarm for a
channel is asserted, and will remain latched until them is cleared by setting bit 4 of address 03h to '1', and then
back to '0'. When the LOS alarm is asserted and register 00h[3]=0b, the xALARM pin will send one interrupt pulse
with a pulse width of approximately 35 ns as shown in
Figure 5-2.
21353-DSH-001-B
Timing of xAlarm Interrupt Signal
Power Supply
Input and Output Buffers
LOS Alarm
DVDDIO
GND
Figure 2-11
Mindspeed Technologies
35 ns
for an illustration of the typical LOS assert/de-assert behavior. The
Figure 5-2
below.
®
Functional Description
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