m21353 Mindspeed Technologies, m21353 Datasheet - Page 30

• Manufacturer Part Number: m21353
• Description: 4.25 Gbps Twelve-channel Backplane Equalizer And Driver With 12x12 Crosspoint Switch
• Manufacturer: Mindspeed Technologies

Table 5-3.
The two wire programming interface is designed to drive 500 pF at 100 and 400 kHz, and 100 pF at 3.4 MHz
operation. During a write operation, data is latched into the M21353 registers on the rising edge of SCL during the
acknowledge phase (ACK) of communication. Refer to the I
that is applicable to the two-wire programming interface.
5.13
With the M21353 configured for Memory Interface Control (MIC) operation, a single M21353 device or an array of
M21353 devices can self configure from a single EEPROM with a two wire serial programming interface upon
device power up.
If the M21353 is configured for MIC operation at power up, the M21353 interface operates as a temporary two wire
quasi-master operating at 100 kHz when downloading from external memory and 400 kHz when configuring other
M21353 devices. In an array of M21353 devices, only one device should be configured for MIC operation, and
subsequent devices in the array should be configured for SIC operation. All devices in an array will receive the
same configuration. When the M21353 device begins to self configure, it will read the contents of an external
EEPROM and configure its registers accordingly. The expected EEPROM device address is 1010000b, and the
M21353 quasi master device address should be set to 0100000b.
Register 01h is used to load the checksum seed value. The checksum seed value should be selected such that the
8 LSB of the sum of the register values from address 00h through 4Ch is equal to 2Eh. After the download from the
EEPROM, the checksum value is computed and written into register address FCh. If the checksum value is equal
to 2Eh, then this is recognized as a valid checksum and the quasi-master device will continue to program other
device on the interface buss. If the checksum value is not equal to 2Eh, the quasi master device will repeat the
download process and look for the correct checksum value up to 512 times before timing out. If the correct
checksum value is not detected, the quasi-master device will not configure any additional devices on the interface
buss.
Register address 02h is used to identify the number of M21353 devices that will be self configured by the quasi
master in MIC mode. When multiple M21353 devices are self configured in an array, the quasi master M21353
device will copy its register contents into other devices in the array sequentially using a 400 kHz interface buss. The
devices in the array must have sequential programming addresses, starting with 0100000b for the quasi master
21353-DSH-001-B
ADDR2
H
H
H
H
H
H
L
L
L
L
L
L
Two Wire Serial Device Address (2 of 2)
Memory Interface Control Mode Operation
ADDR1
H
H
H
H
H
H
L
L
L
L
L
L
Mindspeed Technologies
ADDR0
L
H
L
H
L
H
L
H
F
F
F
F
2
C buss specification standard for timing information
M21353 Device Address
®
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
Functional Description
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
SIC mode
Mode
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