s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 172

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

172
Page Mode READ Operation
Burst-Mode Operation
Summary
When a CellularRAM device is configured for page mode operation, the address
inputs are used to accelerate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than the t
of 4µs during a READ operation, the system must allow t
otherwise be expected) for all subsequent intrapage accesses until CE# goes
HIGH.
When configured for burst-mode operation, it is necessary to allow the device to
perform a refresh within any 4µs window. One of two conditions will enable the
device to schedule a refresh within 4µs. The first condition is when all burst op-
erat ions complet e within 4µs. A burst completes when the CE# signal is
registered HIGH on a rising clock edge. The second condition that allows a refresh
is when a burst access crosses a row boundary. The row-boundary crossing
causes WAIT to be asserted while the next row is accessed and enables the
scheduling of refresh.
CellularRAM products are designed to ensure that any possible asynchronous tim-
ings do not cause data corruption due to lack of refresh. Slow bus timings on
asynchronous WRITE operations require that t
bus timings during asynchronous page READ operations cause the next intrapage
READ data to be delayed to t
Burst mode timings must allow the device to perform a refresh within any 4µs
period. A burst operation must either complete (CE# registered HIGH) or cross a
row boundary within 4µs to ensure successful refresh scheduling. These timing
requirements are likely to have little or no impact when interfacing a CellularRAM
device with a low-speed memory bus.
ADDRESS
LB#/UB#
DATA- I N
WE#
CE#
Figure 63. Extended WRITE Operation
A d v a n c e
AA
.
CellularRAM Type 2
t CEM or t TM > 4 µs
I n f o r m a t i o n
t WP > t WC (MIN)
t DW > t WC (MIN)
WP
and t
DW
AA
be lengthened. Slow
CEM
(not t
maximum time
APA
, as would
cellRAM_00_A0 October 4, 2004