s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 94

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s71gs256nc0bawak0

Manufacturer Part Number
s71gs256nc0bawak0
Description
Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
Manufacturer
Meet Spansion Inc.
Datasheet
AC Characteristics
Hardware Reset (RESET#)
Notes:
1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the
2. Next generation devices may have different reset speeds.
94
JEDEC
RESET# pin needs to be held low only for 100µs for power-up.
Parameter
CE#, OE#
CE#, OE#
RESET#
RESET#
RY/BY#
RY/BY#
t
t
Std.
Ready
Ready
t
t
t
t
RPD
RH
RB
RP
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
RESET# Pulse Width
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/ BY# Recovery Time
Reset Timings NOT during Embedded Algorithms
t
Ready
t
t
Reset Timings during Embedded Algorithms
RP
RP
S29GLxxxN MirrorBit
Description
Figure 13. Reset Timings
A d v a n c e
t
Ready
t
RH
TM
Flash Family
I n f o r m a t i o n
t
RH
Max
Max
Min
Min
Min
Min
t
RB
Speed (Note 2)
S29GLxxxN_MCP_A1 December 15, 2004
500
500
20
50
20
0
Unit
ns
ns
ns
ns
µs
ns

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