s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 179

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

December 15, 2004 cellRAM_02_A0
Partial Array Refresh
Deep Power-Down Operation
Configuration Register Operation
frequent refresh operations to maintain data integrity as temperatures increase.
More frequent refresh is required due to the increased leakage of the DRAM's ca-
pacitive storage elements as temperatures rise. A decreased refresh rate at lower
temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C ,
+ 45°C , + 70°C , and +85°C. The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. If the case temper-
ature is +50°C , the system can minimize self refresh current consumption by
selecting the + 70° C setting. The +15° C and + 45° C settings would result in inad-
equate refreshing and cause data corruption.
Partial array refresh (PAR) restricts refresh operation to a portion of the total
memory array. This feature enables the system to reduce refresh current by only
refreshing that part of the memory array that is absolutely necessary. The refresh
options are full array, three-quarters array, one-half array, one-quarter array, or
none of the array. Data stored in addresses not receiving refresh will become cor-
rupted. The mapping of these partitions can start at either the beginning or the
end of the address map (T ables 5 and 6). READ and WRITE operations are ignored
during PAR operation.
The device can only enter PAR mode if the SLEEP bit in the configuration register
has been set HIGH (CR[4] = 1). PAR is initiated by bring the ZZ# pin to the LOW
state for longer than 10µs. Returning ZZ# to HIGH will cause an exit from PAR
and the ent ire array will be immediat ely available for READ and WRITE
operations.
Deep power-down (DPD) operation disables all refresh-related activity. This mode
is used when the system does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted when DPD is entered. When
refresh activity has been re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal operations can resume.
READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4]
= 0). DPD is initiated by bringing the ZZ# pin to the LOW state for longer than
10µs. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150µs
initialization process. During this 150µs period, the current consumption will be
higher than the specified standby levels but considerably lower than the active
current specification.
Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit
in the CR has been set HIGH (CR[4] = 1).
The configuration register (CR) defines how the CellularRAM device performs its
transparent self refresh. This register is automatically loaded with default settings
during power-up and can be updated anytime while the device is operating in a
standby state.
The CR is loaded using a WRITE operation immediately after ZZ# makes a HIGH-
to-LOW transition
latched into the CR on the rising edge of CE# or WE# , whichever occurs first. Al-
A d v a n c e
(Figure
69). The values placed on addresses A[21:0] are
I n f o r m a t i o n
CellularRAM-2A
179