txc-03108 TranSwitch Corporation, txc-03108 Datasheet
txc-03108
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txc-03108 Summary of contents
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... Enterprise Drive Shelton, Connecticut 06484 • • • Fax: 203-926-9453 • T1Fx8 Device 8-Channel T1 Framer TXC-03108 TECHNICAL OVERVIEW SYSTEM (TERMINAL) SIDE NRZ Data and Signaling Highways System I/O Clocks 3 Monitor Interface Document Number: TXC-03108-MA Ed. 2, May 2001 USA • www.transwitch.com ...
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... Example T1Fx8 TXC-03108 ATM Applications ..................................................... 11 3 T1Fx8 TXC-03108 Block Diagram ......................................................................... 12 4 T1FX8 TXC-03108 208-Lead Plastic Ball Grid Array Package Diagram ............... 17 5 T1FX8 TXC-03108 256-Lead Plastic Ball Grid Array Package Diagram ............... 18 TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW TABLE OF CONTENTS LIST OF FIGURES - ...
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... T1Fx8 to count externally detected code violations or to incorporate an external loss of clock/signal detector. The interface contains a serial port, which can directly control the external line interface unit and other components using the industry standard 'host' mode for device control. TECHNICAL OVERVIEW - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... Although many advanced features are included, the device is optimized for the multichannel application. Sys- tem I/O is minimized, and peripheral functions requiring significant logic or I/O have been reduced or elimi- nated. This device is well suited to systems requiring many T1 interfaces where real estate premium and power consumption is important. TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW 15 ...
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... Transmit framing pulse option (3 ms, 1.5 ms, or 125 s) using TNEGn/TDRVn lead Clock polarity selection for receive line clock input and transmit line clock output NRZ data inversion and clock edge options (separate transmit and receive control) TECHNICAL OVERVIEW - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... DS0 channels Current delay (1.3 s resolution) plus read and write pointer values Microprocessor recentering option DS1 freeze option DS0 channel individual freeze option with microprocessor write capability Framing bit freeze option with microprocessor rewrite capability TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW - ...
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... Shadow registers and counters • Full control of framing, alarm generation and propagation, codec features • HDLC link control, signaling access/control, DS0 access/control • Reset, resync, slip buffer and frame bit access TECHNICAL OVERVIEW - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... Ability to tristate all outputs for in-circuit testing with a single control lead. • Synchronization start position is programmable to any receive or transmit bit position on the sys- tem side to any one of 256 positions • External shadow register clock input TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW - ...
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... PRBS: Per channel generator/analyzer QRSS, 32 bit word, option for 56 kbit kbit/s framed and un-framed DS0 • System Bus: MVIP and Transmission mode (like QT1F- Plus ) with H-MVIP and Data modes which are only on the T1Fx8 TECHNICAL OVERVIEW - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... Applications STo 0-7 Crosspoint (Signaling) Signaling Signaling (Signaling) Time Space Switch Time Space Switch PHAST-3N SONET STS-3 TXC-06103 Figure 1. Example T1Fx8 TXC-03108 T1, Fractional T1, and DS0 Applications TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW RTCLKx8 RTCLKx8 RTDATx8 RTDATx8 T1Fx8 T1Fx8 RTFRMx8 RTFRMx8 HDLC TTCLKx8 ...
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... Proprietary TranSwitch Corporation Information for use Solely by its Customers DS1 LIU T1Fx8 TXC-03108 DS1 LIU COBRA UTOPIA Interface TXC-05427B UTOPIA-2 COBRA TXC-05427B Figure 2. Example T1Fx8 TXC-03108 ATM Applications TECHNICAL OVERVIEW CDB TXC-05150 UTOPIA/FIFO Interface for fractional T1 ATM application CDB TXC-05150 T1Fx8 DS0+SIG, Clock & Frame TXC-03108 2 ...
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... Note: For 208-lead PBGA, the Line Interface Control and Monitor Interface Control share leads based on the ESPBMON bit state, and TTSIGn/RTSIGn share leads with TTAUXn/RTAUXn based on the FTIM bit state. Figure 3. T1Fx8 TXC-03108 Block Diagram TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW ...
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... RTCLKn. A phase shift between the two clocks is detected in this block and a dele- tion or repetition of one frame of data (24 DS0 channels) is provided when the buffer reaches an almost full or almost empty condition, respectively. Microprocessor access to a delay register (difference between write and read pointers) TECHNICAL OVERVIEW - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... Mode or the transmit system clock (TTCLKn) in Transmission or Data Modes. A phase shift between the two clocks is detected in this block, and a deletion or repetition of one frame of data (i.e., 24 DS0 channels) is provided when the buffer reaches an almost full or almost empty condition, respectively. Microprocessor TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW ...
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... An option is provided which permits inter- rupt polarity inversion. An external system clock (SYSCI) is used to run the internal state machines. TECHNICAL OVERVIEW 15 -1 patterns. The other Generator and Analyzer support the - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... BGA thermal resis- tance: junction to ambient POWER REQUIREMENTS Parameter Min V 3. (outputs loaded (outputs loaded (outputs loaded (outputs loaded) DD TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW Symbol Min Max V -0.3 +3 -0.5 5 -55 150 S T -40 85 ...
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... Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° angle, or chamfered for A1 identification. 3. Size of array 16, JEDEC code MO-151-AAF-1 Figure 4. T1FX8 TXC-03108 208-Lead Plastic Ball Grid Array Package Diagram TECHNICAL OVERVIEW Bottom View 16 15 ...
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... Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° angle, or chamfered for A1 identification. 3. Size of array 20, JEDEC code MO-151-BAL-2. Figure 5. T1FX8 TXC-03108 256-Lead Plastic Ball Grid Array Package Diagram TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW ...
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... Proprietary TranSwitch Corporation Information for use Solely by its Customers ORDERING INFORMATION Part Number: TXC-03108AIOG Part Number: TXC-03108AIBG RELATED PRODUCTS TXC-02020, ART VLSI Device (Advanced STS-1/DS3 Receiver/Transmitter). ART per- forms the transmit and receive line interface functions required for transmission of STS-1 (51.840 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. ...
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... Terminator) This PHAST-3N VLSI device provides a COMBUS interface for downstream devices and operates from a power supply of 3.3 volts. TXC-06125, XBERT VLSI Device (Bit Error Rate Generator/Receiver). Programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability. TXC-03108-MA Ed. 2, May 2001 TECHNICAL OVERVIEW - ...
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... TranSwitch covering or relating to any combination, machine, or process in which such semi- conductor products or services might be or are used. TECHNICAL OVERVIEW - NOTES - - T1Fx8 TXC-03108 TXC-03108-MA Ed. 2, May 2001 ...
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... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - • • Fax: 203-926-9453 www.transwitch.com ...
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... Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453. TECHNICAL OVERVIEW Ext.: ____________ Fax: __________________________ Name __________________ __________________ __________________ __________ __________ __________ __________ - T1Fx8 TXC-03108 __________ __________ __________ __________ TXC-03108-MA Ed. 2, May 2001 ...
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... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...