txc-03456 TranSwitch Corporation, txc-03456 Datasheet

txc-03456

Manufacturer Part Number

txc-03456

Description

Device Level Mapper

Manufacturer

TranSwitch Corporation

Datasheet

1.TXC-03456.pdf (96 pages)

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FEATURES

U.S. Patents No.: 4,967,405; 5,040,170; 5,265,096; 5,548,534

U.S. and/or foreign patents issued or pending

TranSwitch and TXC are registered trademarks of TranSwitch Corporation

• Maps an asynchronous 139.264 Mbit/s tributary

• Nibble or byte 139.264 Mbit/s line interface

• SDH/SONET bus access

• SDH/SONET timing mode

• Microprocessor access

• POH byte processing

• Enhanced desynchronizer access

• Testing features

• Boundary scan capability (IEEE 1149.1)

• 144-pin plastic quad flat package

into an AU-4/VC-4 STS-3c/SPE.

SDH/SONET SIDE

- G.751 receive and transmit performance

- Drop/add byte buses

- Optional drop bus AU-4 pointer tracking with

- Drop bus timing

- Add bus timing

- External timing with framing delay

- Intel I/O with separate address/data buses

- Motorola I/O with separate address/data

- Motorola I/O with multiplexed bus

- Interrupt capability with individual mask bits

- Line loopback

- SDH/SONET loopback

- 2

monitoring (frame alignment, distant alarm

indication)

framing delay compensation

compensation

buses

2000 TranSwitch Corporation

TranSwitch Corporation

-1 test generator and analyzer

Drop Bus

Add Bus

Tel: 203-929-8810

Interface

“O”-Bits Indication

•

3 Enterprise Drive

Interface

•

POH

Level 4 Mapper

Fax: 203-926-9453

Alarm

Port

TXC-03456

Control

VCXO

L4M

DESCRIPTION

The L4M device maps a 139.264 Mbit/s asynchronous

line signal into an AU-4 VC-4/STS-3c SPE signal. The

SDH/SONET signal is transmitted via the add bus with

timing derived from the drop bus, add bus, or external

clock source. The L4M can compensate for up to a

frame offset when using external timing and an external

C1 pulse. An option is provided to generate TOH bytes,

such as the A1 and A2 framing bytes, a C1 byte, and the

H1 and H2 pointer bytes only in drop bus and external

timing modes. The VC-4/SPE can be fixed to a known J1

reference when add bus timing is selected, or it can be

positioned with a pointer value of 0 or 522 when drop

bus or external timing is selected.

In the drop direction, an optional pointer tracking

machine is provided. In this mode, the L4M can compen-

sate for up to a frame in offset. External access is pro-

vided for the POH bytes, in addition to internal

processing capability. Serial access is provided for the

overhead communications bits in the format. An alarm

indication port is provided for ring configuration applica-

tions.

• Add/drop multiplexers

• Digital cross-connect systems

• Broadband switching systems

• Transmission equipment

APPLICATIONS

Control

•

Boundary

Scan

Shelton, Connecticut 06484

•

I/O

www.transwitch.com

Transmit Nibble

Transmit Clock In

Receive Nibble

Receive Clock Out

Receive Clock In

or Byte Data

Level 4 Mapper

•

L4M Device

Ed. 1A, January 2000

DATA SHEET

Document Number:

LINE SIDE

USA

TXC-03456

TXC-03456-MB

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