txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 46

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Receive 140 Mbit/s Line AIS Generation
The L4M provides two techniques for generation of line AIS. The first approach uses an external clock, and the
second approach uses a bit stuffing technique. The use of an external stable clock for AIS permits the receive
performance monitoring circuit to be used (i.e., Receive AIS Detector and Receive Frame Alignment Detector),
while the bit stuffing AIS approach disables the receive performance monitoring circuit when the L4M is gener-
ating a receive line AIS. Line AIS is defined as all ones in the data signal. In addition, in the receive direction,
when BSAISE=1 line AIS cannot be generated when the drop bus clock is lost, since this clock is required for
generating line AIS. When the bit stuffing AIS approach is not used and the L4M generates an RXAIS signal,
the external PLL will lose lock. In this case the AISIND pin can be used with some external logic to cause the
external 139.264 MHz VCXO to lock onto the AIS clock to maintain proper synchronization of the 139.264 MHz
VCXO clock.
Using an external clock for AIS generation is enabled by writing a 0 to control bit BSAISE (bit 0 in 1CH). Please
note that control bit BSAISE is 0 upon power-up. The AIS clock is either 17.408 MHz for byte operation, or
34.816 MHz for nibble operation. The AIS clock is monitored for operation and an alarm indication (LAISC) pro-
vided when this clock is not functioning. Loss of AIS clock also prevents the L4M from generating a line AIS in
either the transmit or receive directions. When the L4M is required to generate either a transmit or receive line
AIS the external AISCK clock input is used as the timebase.
The bit stuffing approach does not require an external clock. The capability to generate line AIS on alarm indi-
cations is enabled by writing a 1 to control bit BSAISE. In the transmit direction, line AIS is generated by bit
stuffing 7/9 of the time using an all ones pattern for data. The actual technique consists of performing stuffing
for the first four rows of the 9 subframes (CCCCC=1, and the S-bit is 0). Frequency justification is performed for
row 5, bit stuffing for rows 6, 7, and 8, followed by frequency justification for row 9. In the receive direction, the
approach is the same, bit stuffing is multiplexed into the format prior to the desynchronizer.
In the transmit direction, line AIS cannot be transmitted when the drop clock is lost in the drop bus timing
modes, in the add bus timing mode when the add bus clock is lost, or when the external clock is lost in the
external timing mode.
Receive and Transmit Performance Monitoring
The L4M provides 139.264 Mbit/s receive and transmit performance monitoring. Performance monitoring
includes frame alignment, providing the status of the remote indication alarm bit, counting framing errors and,
when enabled, works in conjunction with the AIS detector circuits.
The L4M monitors the receive and transmit data for frame alignment as specified in ITU-T Recommendation
G.751. The frame structure consists of 2928 bits, starting with bit 1. The frame alignment pattern is carried in
bits 1 through 12, and has the following frame alignment pattern: 111110100000. After frame alignment, a
16-bit performance counter counts the number of errored frames (one or more bits in the frame alignment pat-
tern is in error) in both the transmit and receive directions. In addition, the status of the distant alarm indication
(bit 13 in the format) is provided. A 1 causes a TDAI alarm (bit 5 in 28/29H), or a RDAI alarm (bit 4 in 28/29H),
and an interrupt if the mask bit is enabled, and the hardware interrupt is enabled. No other action is taken upon
detection of Distant Alarm Indication. An enable bit (LFAISE) is provided to generate a 140 Mbit/s AIS, when
loss of frame alignment is detected. The frame alignment detection can be coupled with the AIS recovery cir-
cuit by setting the FDAEN control bit to 1.
In the receive direction, the performance monitoring circuit (i.e., Receive AIS Detector and Receive Frame
Alignment Detector) is disabled when the bit stuffing AIS feature is enabled and the L4M is generating a
receive line AIS; also, the receive frame error counter is inhibited on a RLOF alarm or DBLOC alarm and the
transmit frame error counter is inhibited on a TLOF alarm.
DATA SHEET
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Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M