txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 71

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
12
13
Bit
7
6
5
4
3
2
1
0
7
6
Symbol
J1COM
CCITT
EXG1
EXZ5
EXZ4
EXZ3
EXH4
EXF2
EXC2
EXJ1
Transmit External Z5 Byte: A 1 enables the Z5 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 6FH to be transmitted.
Transmit External Z4 Byte: A 1 enables the Z4 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 6EH to be transmitted.
Transmit External Z3 Byte: A 1 enables the Z3 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 6DH to be transmitted.
Transmit External H4 Byte: A 1 enables the H4 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 6CH to be transmitted.
Transmit External F2 Byte: A 1 enables the F2 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 6BH to be transmitted.
Transmit External G1 Byte: A 1 enables the G1 byte from the external
POH interface to be transmitted. A 0 selects the states of the G1 byte to
be written by internal logic, or by the microprocessor, as enabled.
Transmit External C2 Byte: A 1 enables the C2 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value in register location 69H to be transmitted.
Transmit External J1 Byte: A 1enables the J1 byte from the external
POH interface to be transmitted. A 0 enables the microprocessor-written
value to be transmitted.
J1 Message Comparison Mode: Works in conjunction with the CCITT
control bit according to the following table:
CCITT
J1 Memory Size: A 1 dimensions the transmit and receive memory seg-
ment size to 16 bytes, while a 0 dimensions the memory segment to 64
bytes.
0
1
1
J1COM
X
0
1
DATA SHEET
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Transmit and receive J1 memory segments are
configured for 64 bytes. Incoming messages are
written in a rotating fashion with no defined start-
ing address.
Transmit and receive J1 memory segments are
configured for 16 bytes. Incoming messages are
written in a rotating fashion with no defined start-
ing address.
Transmit and receive J1 memory segments are
configured for 16 bytes. J1 incoming message
comparison feature enabled. The microprocessor
writes the expected 16-byte message into RAM.
After multiframe alignment is established, the J1
bytes in the message are compared against the
microprocessor-written bytes, located in register
location F0 to FFH.
Action
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M