txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 42

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

The following table lists the control states associated with the SS-bits.
Path AIS and loss of pointer alarms are provided. In addition, pointer increments, decrements, and NDFs are
counted in 8-bit performance counters.
Upstream Receive AIS Indication
An upstream AIS indication can be provided for the L4M in one of two ways: using the E1 byte in the Transport
Overhead bytes, or control lead indications. The upstream AIS indication can generate a 140 Mbit/s line AIS
and transmit path RDI, when enabled. Writing a 0 to control bit EAPE enables using the E1 byte for the
upstream AIS indication. For example, the TranSwitch SOT-3 generates an AIS signal (all ones) in the E1 byte
when a loss of frame, loss of signal, loss of pointer, or line or path AIS are detected. The L4M uses majority
logic (five out eight ones) to determine if the E1 byte has an AIS indication (E1AIS alarm). The first and subse-
quent indications indicate the alarm condition. Recovery occurs on the first indication that the E1 byte does not
have an all ones (AIS) state. This indication is to be used by the L4M to generate a receive AIS indication and
path RDI, when enabled.
When a 1 is written to the EAPE control bit it disables the detection of all ones in the E1 byte, and enables the
ISTAT and PAIS leads. An active high on the ISTAT or PAIS lead causes the XISTAT and XPAIS alarms, and a
140 Mbit/s line AIS and path RDI when enabled.
Receive Path Overhead Byte Processing
The Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, Z3, Z4, and the Z5 bytes. All POH bytes are
provided at the external POH interface, including the B3 byte. The POH bytes are also written into the L4M
memory map for a microprocessor read cycle.
Path Overhead Byte Processing is inhibited (and functions reset) when an active low is placed on the POHDIS
lead (pin 19). POH processing (for C2 and J1) is also inhibited when any of the following alarms are detected:
RPSDS
0
0
1
- Drop Bus of the J1 pulse (DBLOJ1) when the PTEN pin is low
- Drop Bus loss of clock (DBLOC)
- E1AIS detected (E1AIS) when EAPE control bit is 0
- PAIS Alarm pin equal to 1 (XPAIS alarm) when EAPE control bit is 1
- ISTAT Alarm pin equal to 1 (XISTAT alarm) when EAPE control bit is 1
- Receive loss of pointer (RLOP) when PTEN pin is high
- Receive path AIS (RPAIS) when PTEN pin is high
RPSSEL
X
0
1
Pointer tracking machine uses 10 as the SS-bit value in the state machine.
Pointer tracking machine uses microprocessor-written value for SS-bit check in
state machine.
SS-bit check in pointer tracking machine disabled. Pointer tracking machine
ignores the SS-bits in the transition state definitions.
DATA SHEET
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Action
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M