txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 81

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
22
23
24
25
Bit
0
7
6
5
4
3
2
1
0
Symbol
RLAISD
XISTAT
ABLOC
DBLOC
1SFOU
XPAIS
XSTAI
RLOC
TLOC
Receive Line AIS Detected: The alarm detection is enabled when control
bit BSAISE is a 0 (bit stuffing AIS disabled), or when BSAISE=1 and the L4M
is not generating a receive AIS based upon received alarms. When control
bit FDAEN is a 0, a 140 Mbit/s line AIS is detected when the receive line sig-
nal (after the desynchronizer) has five or less zeros in two consecutive frame
periods. Recovery occurs if each of the two consecutive frame periods has
six or more zeros. When control bit FDAEN is a 1, an alarm occurs when the
receive line signal has five or less zeros in two consecutive periods, and loss
of frame has occurred. Recovery occurs if each of two consecutive frame
periods has six or more zeros, or frame alignment has been detected.
Transmit Loss Of Clock: An alarm occurs when the transmit line clock
(TXC) is stuck high or low for 13-34 or more consecutive clock cycles of the
RAM clock (RAMCI). Recovery occurs on the first clock transition.
Add Bus Loss Of Clock: An alarm occurs when the add bus input clock
(ACLK) in the add bus timing mode is stuck high or low for 13-34 or more
consecutive clock cycles of the RAM clock (RAMCI). Recovery occurs on the
first clock transition.
Drop Bus Loss Of Clock: An alarm occurs when the drop bus input clock
(DCLK) is stuck high or low for 13-34 or more consecutive clock cycles of the
RAM clock (RAMCI). Recovery occurs on the first clock transition.
Receive Line Loss Of Clock: An alarm occurs when the receive line input
clock (RXCI) is stuck high or low for 12-35 or more consecutive clock cycles
of the RAM clock (RAMCI). Recovery occurs on the first clock transition.
First Stage FIFO Overflow or Underflow: An alarm occurs when the 1st
stage receive FIFO in the desynchronizer has either underflowed or over-
flowed. The FIFO is recentered automatically. No other action is taken. The
1st stage FIFO will overflow or underflow if the value in register 1AH and
1BH is too large, such that the pointer movements are not leaked out as fast
as they are arriving.
SDH/SONET Network Alarm Indication: An indication occurs when an
active high is present on the STAI pin. When control bits XRDIEN and
RDIEN are set to 1, a path RDI is transmitted for the duration of the alarm.
External SDH/SONET Alarm: An indication occurs when an active high is
present on the ISTAT pin. When control bit EAPE is a 1, path RDI is transmit-
ted and a receive AIS is generated for the duration of the alarm.
External Path AIS Alarm: An indication occurs when an active high is
present on the PAIS pin. When control bit EAPE is a 1, path RDI is transmit-
ted and a receive AIS is generated for the duration of the alarm.
DATA SHEET
- 81 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M