txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 17

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

MADBUS
Symbol
DTACK
RAMCI
MOTO
RDY/
INT/
IRQ
WR
DS
Pin No.
57
51
50
73
60
53
I/O/P
O
O
I
I
I
I
TTL8mA
TTL4mA
3-state
CMOS
Type
TTL
TTL
TTL
Write (Intel mode):
Intel Mode - An active low signal generated by the microproces-
sor for writing to the Mapper RAM locations.
Motorola Mode - Not used. For the multiplex mode, this lead is
used for the Data Select control.
Ready (Intel mode) or Data Transfer Acknowledge
(Motorola modes): This lead is three-stated.
Intel Mode - A high is an acknowledgment from the addressed
RAM location that the transfer can be completed. A low indi-
cates that the L4M cannot complete the transfer cycle, and
microprocessor wait states must be generated.
Motorola and multiplex Mode - During a read bus cycle, a low
signal indicates that the information on the data bus is valid.
During a write bus cycle, a low signal acknowledges the accep-
tance of data.
Interrupt:
Intel Mode - A high on this output pin signals an interrupt
request to the microprocessor.
Motorola Mode - A low on this output pin signals an interrupt
request to the microprocessor.
Motorola/Intel Microprocessor Select: This lead works in
conjunction with the MADBUS lead. A high selects a Motorola
microprocessor compatible bus interface. A low selects the Intel
microprocessor compatible bus interface. The following table
summarizes the microprocessor selection.
MOTO
Multiplexed Address/Data Bus: When the MOTO lead is high,
a high on this lead selects a Multiplexed Address/Data Bus
interface, while a low selects separate Address/Data buses.
This lead is disabled when MOTO is low.
RAM Clock Input: Asynchronous clock input used for the inter-
nal L4M RAM operation. This clock must be connected to the
microprocessor clock that has an operating rate of between 12
and 25 MHz with a duty cycle of 50
used as an internal time base for the loss of signal detectors.
0
1
1
DATA SHEET
- 17 -
MADBUS
X
0
1
Intel Microprocessor Interface,
separate address/data buses.
Motorola Microprocessor Interface, sepa-
rate address/data buses.
Motorola Microprocessor Interface, multi-
plexed address/data buses.
Name/Function
Action
10%. This clock is also
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M