txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 70

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
11
Bit
3
2
1
0
RAISEN
Symbol
RAISG
RINVC
EAPE
External Alarm Pin Enable: A 1 enables the external ISTAT (pin 37)
and PAIS (38) pins to function in place of the E1 byte AIS detection cir-
cuit (out of band AIS indication). A 0 disables the external alarm pins
and enables the E1 byte AIS detection circuit (in band AIS indication).
The E1 byte may be used to carry an in band upstream AIS indication.
The E1 byte AIS detection circuitry uses majority logic to determine if
the byte is carrying an AIS indication.
Receive Line AIS Enable: A 1 enables internal (and external) alarms to
generate a receive 140 Mbit/s line AIS. A 0 disables the ability of the
internal alarms to generate a 140 Mbit/s line AIS. The following table is a
summary of the various conditions that generates a 140 Mbit/s line AIS,
and provides an AIS indication (pin 24).
- RAISEN is a 1:
- RAISEN is a 0:
- Receive loss of line frame alignment (RLOF), when LFAISE is a 1 and
Generate Receive AIS: A 1 causes a receive 140 Mbit/s line AIS to be
generated independent of the internal alarms. Note: The microprocessor
may write to control bit RAISG at any time for generating a line AIS.
However, writing a 0 to RAISEN prevents contention between the inter-
nal alarms and the microprocessor for generation of line AIS.
Receive Invert Line Clock: Byte- or nibble-wide data is clocked out of
the L4M on negative transitions of the clock (RXCO) when this bit is a 0.
A 1 enables the byte or nibble line signal to be clocked out of the L4M on
positive transitions of the clock.
BSAISE is a 0.
- Low on EXAIS (pin 17)
- E1 byte AIS indication, when EAPE is a 0
- High on ISTAT (pin 37), when EAPE is a 1
- High on PAIS (pin 38), when EAPE is a 1
- Drop bus loss of J1 alarm (DBLOJ1) when PTEN (pin 2) is low
- Drop bus loss of clock (DBLOC), when BSAISE is a 0
- Path signal label mismatch (PSLERR), when PSLEN is a 1
- Unequipped status (C2EQ0), when PSLEN is a 1
- J1 loss of lock (J1LOL), when J1LEN is a 1
- J1 trace message mismatch (J1TIM), when J1TEN is a 1
- Loss of pointer (RLOP), when PTEN (pin 2) is high
- Path AIS (RPAIS), when PTEN (pin 2) is high.
- The microprocessor writes a 1 to RAISG.
Note. The microprocessor may write to control bit RAISG at any
time to generate a line AIS. However, writing a 0 to RAISEN pre-
vents contention between the internal alarms and the micropro-
cessor for generation of line AIS.
DATA SHEET
- 70 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M