txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 87

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

PERFORMANCE COUNTERS DESCRIPTIONS
All performance counters globally can be configured to be either saturating or non-saturating with a roll over in
count. Writing a 1 to control bit COR (bit 0 in register location 13H) conditions all counters to be non-saturating.
Reading a non-saturating counter will not clear the counter. When the counters are configured to be saturating,
the counter will clear on a microprocessor read cycle. All performance counters are cleared simultaneously
when a 1 is written to control bit RSETC. This bit is self clearing and does not require a 0 to be written to it.
When reading a 16-bit counter, the low order byte must be read first.
Address
Address
F0 to FF
40
41
42
43
44
45
46
47
48
49
7-0
7-0
7-0
7-0
7-0
7-0
Bit
Bit
Compare
Message
Symbol
Analyzer
Transmit
Framing
Framing
Symbol
Counter
Counter
Counter
Counter
Receive
Counter
FEBE
Error
Error
J1
B3
Path Trace Message Compare feature: The microprocessor writes into this
16-byte memory segment the expected J1 message (multiframe bits and
CRC as required) when CCITT is 1 and J1COM is 1. This message is then
compared against the received J1 byte for the correct message. The starting
address of the message must be written to location F0H (multiframe value of
1). The L4M performs the alignment of the incoming message against this
message segment.
B3 Byte Parity Error 16-bit counter: Counts the number of B3 BIP-8
parity error indications that have been detected between the received B3
value and the calculated value. The low order counter value is held in
location 40H. The high order counter value is in held in location 41H. Bit 0
in 40H is the LSB.
Far End Block Error 16-bit Counter: When control bit FEBEBC is a 0,
this counter counts the number of FEBE error count indications received in
bits 1 through 4 of the G1 byte. The maximum number of errors counted
per frame is 8. Values other than between 1 thru 8 are counted as 0 errors.
The low order counter value is held in location 42H. The high order
counter value is in held in location 43H. When control bit FEBEBC is a 1,
the number of FEBE blocks in error are counted instead of the FEBE
count. Bit 0 in 42H is the LSB.
Analyzer 16-bit Error Counter: Enabled when control bit ANAEN is a 1,
and when the analyzer is in lock. Counts the number of errors received in
the received 2
location 44H. The high order counter value is in held in location 45H. Bit 0
in 44H is the LSB.
Transmit 140 Mbit/s Framing Pattern 16-bit Error Counter: After frame
alignment, this counter counts the number of transmit errored framing pat-
terns in the G.751 signal. The low order counter value is held in location
46H. The high order counter value is in held in location 47H. Bit 0 in 46H is
the LSB.
Receive 140 Mbit/s Framing Pattern 16-bit Error Counter: Enabled
when control bit BSAISE is a 0 or when BSAISE is 1 and the L4M is not
generating a receive AIS. After frame alignment, this counter counts the
number of received errored framing patterns in the G.751 signal. The low
order counter value is held in location 48H. The high order counter value is
in held in location 47H. Bit 0 in 48H is the LSB.
23
-1 PRBS pattern. The low order counter value is held in
DATA SHEET
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Description
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M