txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 84

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

TRANSMIT POH REGISTER DESCRIPTIONS
The transmission of the POH byte in the add direction, and the processing of the POH bytes in the drop direc-
tion are enabled when a high is placed on the POHDIS lead.
Address
Address
6A
68
69
34
7-0
7-0
7-0
Bit
Bit
7
6
5
4
3
2
C2 Signal
Transmit
B3 Error
Symbol
G1 Byte
Mask
Label
Symbol
RPAIS
RLOF
RLOP
TLOF
RDAI
TDAI
B3 Error Mask and Test Byte: When control bit TESTB3 is written with a 0,
a 1 written to any of the bit locations will generate a continuous bit error in
the corresponding B3 bit position. Internally, this RAM location is exclusive-
or gated with the calculated B3 byte prior to transmission. The B3 errors are
transmitted until this location is rewritten with a 00H. Bit 7 in this location cor-
responds to bit 1 in the transmitted B3 byte. When control bit TESTB3 is writ-
ten with a 1, the bits written into this location are transmitted as the B3 byte.
C2 Signal Label Byte: When control bit EXC2 is a 0, the bits written into this
location are transmitted as the C2 byte. When control bits EXC2 and
POHRAM are a 1, the external POH interface C2 byte is written into this
location, and is also transmitted. When control bit EXC2 is a 1, and
POHRAM is a 0, the external POH interface C2 byte is transmitted and this
location holds the microprocessor-written C2 value. Bit 7 in this location cor-
responds to bit 1 in the transmitted C2 byte.
Transmit G1 Byte: Bits 7-0 provide the states of the external POH byte or
microprocessor-written values, according to the following:
1
7
When control bits EXG1, RDIEN, and FEBEEN are 0, the microprocessor
writes the transmitted FEBE state and path RDI state. The unassigned bits
are always written by the microprocessor unless EXG1 is a 1. When control
bits EXG1 and POHRAM are a 1, the external POH interface G1 byte is writ-
ten into this location, and is also transmitted. When control bit EXG1 is a 1,
and POHRAM is a 0, the external POH interface G1 byte is transmitted and
this location holds the microprocessor-written G1 value. The unassigned bits
for transmission must always be written into bits 2 through 0 in this location,
otherwise the transmitted states of these bits are undetermined. See also
FEBEEN, RDIEN and RING control bits.
2
6
FEBE
Transmit 140 Mbit/s Loss Of Frame alarm
Receive 140 Mbit/s Loss Of Frame alarm
Transmit 140 Mbit/s Distant Alarm Indication
Receive 140 Mbit/s Distant Alarm Indication
Receive Loss Of Pointer
Receive Path AIS
3
5
4
4
RDI Unassigned
5
3
DATA SHEET
- 84 -
6
2
7
1
8 G1 Byte
0 This location
Description
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M