txc-03108 TranSwitch Corporation, txc-03108 Datasheet - Page 14

• Manufacturer Part Number: txc-03108
• Description: 8-channel Framer
• Manufacturer: TranSwitch Corporation

Ed. 2, May 2001
T1Fx8
TXC-03108
TXC-03108-MA
as well as the read and write pointers is also provided. The framing bits may either be slipped or not as an option; when
the framing bits are slipped and the receive framer is disabled, a non-SF or ESF T1 signal can be retimed but passed
intact through the T1Fx8. Slip alarm indications are provided for the microprocessor. The receive slip buffer may be
recentered by the microprocessor, or automatically. Individual DS0s can be accessed by the microprocessor for the
insertion or detection of system idle, test pattern or out of service codes. When the receive slip buffer is bypassed, the
receive clock (RTCLKn) and data (RTDATn and RTSIGn) are provided as outputs, along with a receive synchronization
signal (RSYNCn).
For 2, 4 or 16-state signaling (robbed-bit signaling), a three times 96-bit signaling buffer is used to store the signaling
bits which have been extracted by the Receive Framer. The signaling buffer may be debounced, read, frozen and writ-
ten to by the microprocessor. This feature permits both signaling to or from the microprocessor (call control) as well as
trunk conditioning under control of the microprocessor. If signaling is disabled for a particular channel, the ABCD sig-
naling bits for that time slot will be frozen in their present states. When a loss of signal or an out of frame condition is
detected, the signaling bits are also automatically frozen in their present states. The signaling bit states are held until
framing has been recovered. For non-switched 56 kbit/s service, the eighth bit of every DS0 may be set to a one. For
GR-253-CORE applications, DS0 alarms are supported for full DS1 applications.
On the terminal side, the system interface interconnects the eight framers with the system. For each framer there is a
separate receive and transmit highway for the Transmission, Data and MVIP interface Modes of operation. The receive
highway consists of a data bus (RTDATn), a signaling bus (RTSIGn), a clock (RTCLKn), and a synchronization signal
(RTFRMn). The transmit highway consists of a data bus (TTDATn), a signaling bus (TTSIGn), a clock (TTCLKn), and a
synchronization signal (TTFRMn). In the Transmission Mode, the system interface operates at 1.544 MHz, with chan-
nels in the data highway, and signaling and alarms on the signaling highway. The receive and transmit system inter-
faces are synchronized by multiframe pulses that occur at 3-millisecond intervals. Twenty-four frames are sent on the
data and signaling highways within the 3-millisecond period, with each of the twenty-four frames consisting of 193-bits
(24 DS0 channels plus the framing bit), which correspond to a DS1 frame. The receive and transmit slip buffers can be
individually bypassed in this Mode. The Data Mode is very similar to the Transmission Mode except that the synchroni-
zation signal occurs every 125 microseconds and the signaling highway carries the all signaling bits as nibbles every
frame.
To support fractional T1 applications in Transmission and Data Modes, a Gapped Clock or Marker pulse may be indi-
vidually programmed for each transmit or receive DS0 (7 or 8 bits wide) and is supplied on leads RTAUXn and
TTAUXn. In addition, an auxiliary data highway is provided and the transmit side system DS0s may come from either
TTDATn, TTAIXn, the Receive Slip Buffer (DS0 loopback), digital milliwatt or programmable idle code which is select-
able on a per DS0 basis.
When the MVIP Mode is selected, the system interface also consists of receive and transmit data highways. However,
the receive and transmit system interfaces are synchronized by pulses occurring at 125-microsecond intervals in this
Mode. The receive and transmit slip buffers must always be enabled in this Mode. Each frame consists of 32 time slots
which carry the DS0 channels in defined time slots on the data highway. The signaling highway also carries 32 time
slots, which contain the signaling states for each channel. RTCLKn and TTCLKn are always inputs at 2.048 MHz.
Gapped clock or Marker pulses and the auxiliary input are not available in this Mode.
The T1Fx8 also supports an H-MVIP/H.100 Mode on the system side. The data and signaling highways from framers
1 through 4, essentially operating in MVIP Mode, are byte-interleaved, sharing the RTDAT1, TTDAT1, RTSIG1 and
TTSIG1 leads; RTCLK1 and TTCLK1 operate at 16.384 MHz with RTFRM1 and TTFRM1 providing either H-MVIP or
H.100 synchronization pulses at 125-microsecond intervals. Framers 5 through 8 share the system side leads for
framer number 5 in a like manner. Gapped clock or Marker pulses and the auxiliary input are not available in this Mode.
A transmit slip buffer is provided to absorb low speed jitter in the transmit data. Each Transmit Slip Buffer block controls
DS0 access and retiming for the framer by using a two-frame buffer that can be optionally bypassed in the Transmis-
sion and Data Mode. When the transmit slip buffer is enabled, transmit DS0s are written into the buffer by the transmit
system clock (TTCLKn), and they are optionally read out from the buffer by the receive clock (RCLKn) or local oscillator
(BPOSC) in any system side Mode or the transmit system clock (TTCLKn) in Transmission or Data Modes. A phase
shift between the two clocks is detected in this block, and a deletion or repetition of one frame of data (i.e., 24 DS0
channels) is provided when the buffer reaches an almost full or almost empty condition, respectively. Microprocessor
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TECHNICAL OVERVIEW
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