uaa3580 NXP Semiconductors, uaa3580 Datasheet - Page 11

• Manufacturer Part Number: uaa3580
• Description: Wideband Code Division Multiple Access Frequency Division Duplex Zero If Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9.3
The RF fractional-N synthesizer is set via the 3-wire bus
with the FRAC and CH chains. CH sets the integer divider
ratio and FRAC the fractional divider ratio. They both
provide the LO frequency in accordance with the following
equation:
Where
Where K
integer value of CH[8:0] and f
reference applied to pin REFIN.
Example: to obtain a f
error less than f
to 1290555 if the reference frequency is 26 MHz. It should
be noted that some particular frequencies can be obtained
in two ways; N
same frequency as N
9.4
9.4.1
The clock PLL is based on the SD fractional-N synthesizer
that allows to derive the UMTS system clock including AFC
from a non-corrected external 26 MHz only GMS
reference. The clock PLL frequency with the AFC
correction word is given by the following equation:
Where
AFC represents the integer value of AFC[11:0] and f
the external reference frequency applied to pin REFIN.
9.4.2
The clock PLL synthesizer is controlled by bits CLKon and
CLKoff. At power-up the clock PLL synthesizer is
automatically on when pin RXCEN is set HIGH. The
control, done with CLKon, will be reset at the rising edge
of RXCEN. For application which do not require the UMTS
clock system, the clock PLL can be powered-down with bit
CLKoff set to logic 1.
2002 Oct 30
f
f
RFLO
CLKPLL
Wideband code division multiple access
frequency division duplex zero IF receiver
RF PLL synthesizer
=
Clock PLL synthesizer
K
K
RX
AFC
=
C
frac(RX)
AFC
f
ref
LOCK
f
is the integer value of FRAC[21:0], N
ref
=
MODE
RX
N
---------- -
PLL
231
--------- -
512
=
PLL
2
RX
= x and K
9
---------------------- -
------- -
2
+
1
22
+
N
+
MODES
RX
K
2
RFLO
RX
K
AFC
------------
AFC
2
frac(RX)
= x
21
must be set to 164 and K
K
frequency of 2.14 GHz with an
frac(RX)
RX
ref
1 and K
+
is the external frequency
1
-- -
2
= 0.25 provides the
frac(RX)
= 0.75
RX
frac(RX)
is the
ref
is
11
Table 4 Clock mode
Notes
1. Hard power-down of the clock PLL done with RXCEN.
2. Power-down achieved via the 3-wire bus, reset by
3. Power-down achieved via the 3-wire bus, no effect by
4. X = don’t care.
9.4.3
The clock PLL output divider ratio is set in accordance with
Table 5.
Table 5 Clock mode; note 1
Note
1. X = don’t care.
RXCEN CLKon CLKoff
CLKoff
X
RXCEN.
RXCEN in this mode. This mode will be reset if V
is not maintained.
1
0
0
0
0
1
0
1
(4)
C
LOCK
CLK1
X
X
0
0
1
1
1
1
0
(4)
PLL
CLK0
OUTPUT DIVIDER
X
0
1
0
1
0
0
0
1
UMTSCLKO output
disabled
clock divider ratio set to
default
clock divider ratio set to 2
clock divider ratio set to 4
clock divider ratio set to 8
CLKPLL synthesizer
enabled (default)
CLKPLL synthesizer
disabled; note 1
CLKPLL synthesizer
disabled; note 2
CLKPLL synthesizer
disabled; note 3
DESCRIPTION
Objective specification
DESCRIPTION
UAA3580
DDD