hi-3584a Holt Integrated Circuits, Inc., hi-3584a Datasheet - Page 12

• Manufacturer Part Number: hi-3584a
• Description: Arinc 429 3.3v Serial Transmitter And Dual Receiver With High-speed Interface
• Manufacturer: Holt Integrated Circuits, Inc.

AC ELECTRICAL CHARACTERISTICS
The HI-3584APCI and HI-3584APCT use a 64-pin plastic
chip-scale package. This package has a metal heat sink
pad on its bottom surface. This heat sink is electrically
connected to the die. To enhance thermal dissipation, the
VDD = 3.3V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz 0.1% with 60/40 duty cycle
HEAT SINK - CHIP-SCALE PACKAGE ONLY
REPEATER OPERATION TIMING
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
CONTROL WORD TIMING
RECEIVER FIFO AND LABEL READ TIMING
TRANSMITTER FIFO AND LABEL WRITE TIMING
TRANSMISSION TIMING
CLK HIGH separation from second
Spacing -
Spacing -
Delay - Start ARINC 32nd Bit to
Delay - ENTX HIGH to 429DO or
Delay - ENTX HIGH to 429DO or
PARAMETER
EN
EN
HIGH to next
HIGH to next
Setup - DATA BUS Valid to
Hold -
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing between Label Write pulses
Spacing - TX/R HIGH to ENTX LOW
Setup - DATA BUS Valid to
Delay -
Delay -
Spacing -
Hold -
Delay - TX/R LOW to ENTX HIGH
CWSTR
Spacing -
Delay -
Delay -
EN
EN
Delay -
EN
Delay -
Hold -
EN
EN
PL
LOW (Same ARINC Word)
pulse HIGH (SEL is HIGH)
Pulse Width -
PL2
LOW (Next ARINC Word)
LOW to DATA BUS Valid
Pulse Width -
HIGH to DATA BUS Hi-Z
HIGH to DATA BUS Hi-Z
HIGH to DATA BUS Hi-Z
PL2
Setup - SEL to
Hold - SEL to
PL1
D/R
EN
HOLT INTEGRATED CIRCUITS
Pulse Width -
PL
D/R
Spacing -
HIGH to ENTX HIGH
EN
429DO
429DO
HIGH to TX/R LOW
HIGH to
rising to
HIGH to
LOW: High Speed
LOW to
LOW to
CWSTR
: High Speed
: Low Speed
EN1
Low Speed
PL1
Pl1
D/R
+
PL2
EN
EN
PL
EN
EN
PL
HI-3584A
CWSTR
or
or
or
HIGH
HIGH
HIGH
HIGH
HIGH
rising
LOW
LOW
LOW
EN2
PL2
PL2
12
heat sink can be soldered to matching circuit board pad.
The heat sink may be connected to GND or left floating.
Do not connect heat sink pad to VDD.
SYMBOL
t
t
t
t
t
t
t
t
t
READEN
t
t
ENDATA
DATAEN
t
t
t
t
t
t
t
t
t
t
CWSTR
CWSET
CWHLD
t
DWSET
DWHLD
ENTX/R
SELEN
ENSEL
CLKEN
PLCYC
ENDAT
ENDAT
D/REN
END/R
t
LABEL
PL2EN
DTX/R
TX/REN
ENEN
t
t
t
t
t
PL12
t
t
TX/R
ENPL
PLEN
D/R
D/R
t
EN
PL
MR
MIN
175
25
25
10
10
50
70
70
25
30
30
10
40
40
5
0
0
0
0
0
0
LIMITS
TYP
t
CLK
MAX
± 1%
128
200
16
25
50
20
30
50
25
-10
UNITS
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns