hi-3189 Holt Integrated Circuits, Inc., hi-3189 Datasheet
hi-3189
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hi-3189 Summary of contents
Page 1
... DEI3182A. Inputs are provided for clocking and synchronization. These signals are AND'd with the DATA inputs to enhance system performance and allow the HI-3189 to be used in a variety of applications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL and CMOS compatibility ...
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... Rate Select CAPA, CAPB Value (pF) Logic “0” 68 Logic “1” 68 Logic “0” 470 Logic “1” 470 DATA (A) CLOCK RATE SELECT SYNC DATA (B) HI-3189 DESCRIPTION B Rise / Fall Time Data Rate 10% - 90% (us) (Kbits/sec) 1.0 - 2.0 100 5.0 - 15.0 12.0 - 14.5 5.0 - 15.0 12.0 - 14.5 N/A N/A Table 2. Rate Select Pin Truth Table ...
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... ARINC 429 bus application: +15V for +VS, -15V for -VS and +5V for both VREF and VLOGIC. The differential output swing of the HI-3189 is equal VREF. Using +5V gives a differential output swing of 10V different output voltage swing is required, an additional power supply is needed to set VREF ...
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... OUT A B Rise Time ( , ) - Low Speed OUT OUT A B Fall Time ( , ) - Low Speed OUT OUT HI-3189 CONDITIONS Voltage between +VS and -VS terminals For ARINC 429 High-temp & Military Industrial 150 us pulse applied through an external 37.5 Ohm resistor Soldering, 60 seconds A -V REF +V ADJUST REF ...
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... Output Voltage Low (Output to Ground) Output Voltage Null Output Impedance Output Short Circuit Current +VS Short Circuit Current -VS Short Circuit Current Note 1. Guaranteed by design, but not tested. Note 2. Tested at DC only. HI-3189 = Operating Temperature Range (unless otherwise specified). A SYMBOL CONDITION I +VS = 16.5V, -VS=-16.5V CC VLOGIC = VREF = 5.5V DATA(A) = CLOCK = SYNC = “ ...
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... No M Yes HOLT INTEGRATED CIRCUITS VLOGIC VREF 2 15 AMPB RATE SELECT 3 14 CLOCK SYNC 4 13 DATA(B) DATA(A) HI-3189 CAPB CAPA 6 11 OUTB OUTA 7 10 AMPA - +VS GND 16 - Pin Cerdip package (See page 1 for additional pin configurations) LEAD Theta ...
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... REVISION HISTORY Revision Date DS-3189, Rev. New 08/22/08 HI-3189 Description of Change Initial Release HOLT INTEGRATED CIRCUITS 7 ...
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... Standard 95) 16-PIN CERAMIC SIDE-BRAZED DIP .125 min (3.175) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-3189 PACKAGE DIMENSIONS .050 max .790 max (1.27 max) .288 ±.005 (7.315 ±.125) .100 BSC (2 ...
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... PIN 1 .040 x 45° 3PLS (1.016 x 45° 3PLS) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-3189 PACKAGE DIMENSIONS .080 ±.020 (2.032 ±.508) .451 ±.009 (11.455 ±.229) .050 BSC (1 ...