am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 25

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

Notes:
1. Upon power-up or hardware reset, the default setting is
2. RDY will default to being active with data when the Wait
3. Assumes even address.
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Handshaking Option
If the device is equipped with reduced wait-state hand-
shaking, the host system should set address bits
A14–A12 to 010 for a clock frequency of 40 MHz or to
0 11 fo r a c l o c k fr eq u e n c y o f 5 4 M H z fo r t h e
system/device to execute at maximum speed.
Table 9
(wait states) for various conditions.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
24
6–11 MHz
12–23 MHz
24–33 MHz
34–40 MHz
40–47 MHz
48–54 MHz
Frequency
seven wait states.
State Setting is set to a total initial access cycle of 2.
Table 8. Programmable Wait State Settings
A14
System
0
0
0
0
1
1
Range
describes the typical number of clock cycles
Table 9. Initial Access Codes
A13
0
0
1
1
0
0
2
2
3
4
4
5
2
3
4
5
5
6
A12
0
1
0
1
0
1
3
4
5
6
6
7
Total Initial Access
4
5
6
7
7
8
Cycles
P R E L I M I N A R Y
2
3
4
5
6
7
40 MHz
54 MHz
Device
Rating
Speed
Am42BDS640AG
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Standard Handshaking Operation
For optimal burst mode performance on devices with
standard handshaking, the host system must set the
appropriate number of wait states in the flash device
depending on the clock frequency.
Table 10
(wait states) for various conditions with A14–A12 set to
101.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
Burst Read Mode Configuration
The device supports four different burst read modes:
continuous mode, and 8, 16, and 32 word linear wrap
around modes. A continuous sequence begins at the
starting address and advances the address pointer
until the burst operation is complete. If the highest
address in the device is reached during the continuous
burst read mode, the address pointer wraps around to
the lowest address.
For example, an eight-word linear burst with wrap
around begins on the starting burst address written to
the device and then proceeds until the next 8 word
boundary. The address pointer then returns to the first
word of the boundary, wrapping back to the starting
location. The sixteen- and thirty-two linear wrap around
modes operate in a fashion similar to the eight-word
mode.
Table 11
four burst read modes.
Table 10. Wait States for Standard Handshaking
Conditions at Address
Initial address is even
Initial address is odd
Initial address is even,
and is at boundary crossing*
Initial address is odd,
and is at boundary crossing*
describes the typical number of clock cycles
shows the address bits and settings for the
Cycles after AVD# Low
Typical No. of Clock
November 1, 2002
40/54 MHz
7
7
7
7