am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 28

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

Unlock Bypass Command Sequence
The unlock bypass feature allows the system to prima-
rily program to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock
bypass mode. The erase command sequences are
four cycles in length instead of six cycles.
“Command Definitions,” on page 30
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Unlock
Bypass Program, Unlock Bypass Sector Erase, Unlock
Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the ACC input. When the system asserts V
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
t w o - c y c l e U n l o c k B y p a s s p r o g r a m c o m m a n d
sequence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 2
ation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 21, “Asynchronous Program Operation Tim-
ings,” on page 51
November 1, 2002
illustrates the algorithm for the program oper-
for timing diagrams.
shows the require-
P R E L I M I N A R Y
Table 14,
Am42BDS640AG
ID
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
“Command Definitions,” on page 30
and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no
longer latched. The system can determine the status of
the erase operation by using DQ7 or DQ6/DQ2. Refer
to the
31
Notes:
1. See Table 14 for erase command sequence.
2. See the section on DQ3 for information on the sector
section for information on these status bits.
erase timer.
“Flash Write Operation Status” section on page
No
Figure 2. Erase Operation
Command Sequence
Erasure Completed
Write Erase
from System
Data = FFh?
Data Poll
START
Yes
shows the address
Embedded
Erase
algorithm
in progress
Table 14,
27