saa4955tj NXP Semiconductors, saa4955tj Datasheet - Page 6

• Manufacturer Part Number: saa4955tj
• Description: 2.9-mbit Field Memory
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Write operation
Write operations are controlled by the SWCK, RSTW, WE
and IE signals. A write operation starts with a reset write
address pointer (RSTW) operation, followed by a
sequence SWCK clock cycles during which time WE and
IE must be held HIGH. Write operations between two
successive reset write operations must contain at least
40 SWCK write clock cycles while WE is HIGH. To transfer
data temporarily stored in the serial write registers to the
memory array, a reset write operation is required after the
last write operation.
R
The first positive transition of SWCK after RSTW goes
from LOW to HIGH resets the write address pointer to the
lowest address ( 12 decimal), regardless of the state of
WE (see Figs 3 and 4). RSTW set-up (t
(t
(see Fig.3). The reset write operation may also be
asynchronously related to the SWCK signal if WE is LOW.
RSTW needs to stay LOW for a single SWCK cycle before
another reset write operation can take place. If RSTW is
HIGH for 1024 SWCK write clock cycles while WE is
HIGH, the SAA4955TJ will enter a built-in test mode and
will not be in regular operation.
R
The SAA4955TJ will enter random write block access
mode if the following signal sequence is applied to control
inputs IE and WE during the first four SWCK write clock
cycles after a reset write (see Figs 5 and 6):
During the first four clock cycles, control signals WE and
IE will function as defined for normal operation. The
remaining 12 bits of the 13-bit write block address must be
applied, in turn, to the selected input pin (D0 or IE) at the
following 12 positive transitions of SWCK. The Least
Significant Bit (LSB) of the write block address is applied
1999 Apr 29
h(RSTW)
ESET
ANDOM WRITE BLOCK ACCESS MODE
At the 1st and 2nd positive transitions of SWCK,
IE must be LOW and WE must be HIGH
At the 3rd and 4th positive transitions of SWCK,
IE must be HIGH and WE must be LOW
At the 5th positive transition of SWCK, the state of WE
determines which input pin is used for the block address.
If WE is LOW the Most Significant Bit (MSB) of the block
address must be applied to the D0 input pin. If WE is
HIGH, the Most Significant Bit (MSB) of the block
address is applied to pin IE.
2.9-Mbit field memory
W
) times are referenced to the rising edge of SWCK
RITE
: RSTW
su(RSTW)
) and hold
6
at the 17th positive transition of SWCK. A write latency
period of 18 additional SWCK clock cycles is required
before write access to the new block address is possible.
During this time, data is transferred from the serial write
and parallel write registers into the memory array and the
write pointer is set to the new block address.
Block address values between 0 and 6143 are valid.
Values outside this range must be avoided because invalid
block addresses can result in abnormal operation or a
lock-up condition. Recovery from lock-up requires a
standard reset write operation.
WE must remain LOW from the 3rd positive transition of
SWCK to the 17th write latency SWCK clock cycle if the
block address is applied to pin D0. If the block address is
applied to pin IE, WE must be HIGH on the 5th positive
transition of SWCK, may be HIGH or LOW on the 6th
transition, and must be LOW from the 7th transition to the
17th write latency SWCK clock cycle.
At the 18th write latency SWCK clock cycle, IE and WE
may be switched HIGH to prepare for writing new data at
the next positive transition of SWCK. The complete write
block access entry sequence is finished after the
18th write latency cycle.
The LOW-to-HIGH transition on RSTW required at the
beginning of the sequence should not be repeated.
Additional LOW-to-HIGH transitions on RSTW would
disable write block address mode and reset the write
pointer.
A
Two different types of memory are used in the data
address area: a mini cache for the first 12 data words after
a reset write or a reset read, and a DRAM cell memory
array with a 245760 word capacity. Each word is 12 bits
long. The mini cache is needed to store data immediately
after a reset operation since a latency period is required
before read or write access to the memory array is
possible. Latency periods are needed for read or write
operations in random read or write block access modes
because data is read from, or written to, the memory array.
The data in the mini cache can only be accessed directly
after a standard reset operation. It cannot be accessed in
random read or write block access modes.
The address area reserved for the mini cache, accessible
after a standard reset operation, is from decimal 12 to 1.
The memory array starts at decimal 0 and ends at 245759.
Decimal address 0 is identical to block address 0000H.
Because a single block address is defined for every
40 words in the memory array, block address 0001H
DDRESS ORGANIZATION
Product specification
SAA4955TJ