mt8lsdt1664hy-13e Micron Semiconductor Products, mt8lsdt1664hy-13e Datasheet - Page 15

• Manufacturer Part Number: mt8lsdt1664hy-13e
• Description: 64mb, 128mb, 256mb X64, Dr 144-pin Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Notes
09005aef8077d63a
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
10.
12. Other input signals are allowed to transition no
13. IDD specifications are tested after the device is
14. Timing actually specified by
11. AC timing and I
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
f = 1 MHz; T
1.4V.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial temperature: 0°C
trial Temperature: -40°C T
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
two AUTO REFRESH command wake-ups should
be repeated any time the
ment is exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V
and no longer at the 1.5V crossover point.
more than once every two clocks and are other-
wise at valid V
properly initialized.
fied as a reference only at minimum cycle rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
OH
SS
IH
and V
and V
is dependent on output loading and cycle
or V
DD
OL
Q must be powered up simultaneously.
SS
IL
. The last valid data element will meet
Q must be at the same potential.) The
(or between V
A
IH
Q
DD
= 25°C; pin under test biased at
or V
tests have V
IL
levels.
t
IL
SS
T = 1ns.
IL
T
A
t
REF refresh require-
.
A
50pF
and V
(MAX) and V
t
CKS; clock(s) speci-
IL
DD
+85°C).
= 0V and V
+70°C and Indus-
, V
IH
DD
) in a mono-
Q = +3.3V;
IH
IH
(MIN)
= 3V,
DD
15
16. Timing actually specified by
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and
31. Refer to component datasheet for timing wavfe-
32. The value of
33. Leakage number reflects the worst case leakage
15. Timing actually specified by
17. Required clocks are specified by JEDEC functionality
30. CKE is HIGH during refresh command period
64MB, 128MB, 256MB (x64, DR)
specified as a reference only at minimum cycle rate.
and are not dependent on any timing parameter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
width
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
t
and is guaranteed by design.
and
(MIN) else CKE is LOW. The I
nominal value and does not result in a fail value.
forms.
ule SPDs is calculated from
possible through the module pin, not what each
memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-133 and -13E.
IH
t
overshoot: V
WR, and PRECHARGE commands). CKE may
t
CK = 7.5ns; for -10E, CL= 2 and
DD
144-PIN SDRAM SODIMM
IL
current will increase or decrease propor-
t
RP) begins 7ns for -13E; 7.5ns for -133
3ns, and the pulse width cannot be
t
(MIN) = -2V for a pulse width 3ns.
CK = 10ns for -10E, and
t
RAS used in -13E speed grade mod-
IH
(MAX) = V
t
CK = 7.5ns; for -133, CL = 3
©2004 Micron Technology, Inc. All rights reserved.
t
RC -
t
t
WR plus
WR.
DD
DD
6 limit is actually a
Q + 2V for a pulse
t
RP = 45ns.
t
CK = 7.5ns for
t
CK = 10ns.
t
RP; clock(s)
IL
under-
t
RFC