mt8lsdt1664hy-13e Micron Semiconductor Products, mt8lsdt1664hy-13e Datasheet - Page 4

• Manufacturer Part Number: mt8lsdt1664hy-13e
• Description: 64mb, 128mb, 256mb X64, Dr 144-pin Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 6:
Pin numbers may not correlate with symbols; for more information refer to the Pin Assignment tables on page 3
09005aef8077d63a
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
23, 24, 25, 26, 115, 116, 117,
11, 12, 27, 28, 45, 46, 63, 64,
75, 76, 91, 92, 107, 108, 119,
57, 58, 59, 60, 72, 77, 78, 79,
3–10, 13–20, 37– 44, 47–54,
70 (256MB), 103, 104, 105,
81, 82, 101, 102, 113, 114,
1, 2, 21, 22, 35, 36, 55, 56,
83– 90, 93–100, 121–128,
70 (64MB, 128MB), 73
29, 30, 31,32, 33, 34,
129, 130, 143, 144
PIN NUMBERS
109, 111, 112
120, 139, 140
65, 66, 67
106, 110
131–138
61, 74
62, 68
69, 71
118
142
141
80
Pin Descriptions
DQMB0–DQMB7
(64MB, 128MB)
RAS#, CAS#,
CKE0, CKE1
DQ0–DQ63
SYMBOL
BA0, BA1
CK0, CK1
(256MB)
S0#, S1#
A0–A11
A0–A12
WE#
DNU
SDA
V
SCL
V
NC
DD
SS
Output
Output
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
–
–
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
Clock: CK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. CK also increments the
internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE, POWER-
DOWN, and SELF REFRESH operation (all device banks idle),
ACTIVE POWER-DOWN (row ACTIVE in any device bank), or CLOCK
SUSPEND operation (burst access in progress). CKE is synchronous
except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CK, are disabled during
power-down and self refresh modes, providing low standby
power.
Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S#
is registered HIGH. S# is considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input data
is masked when DQMB is sampled HIGH during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency)
when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array
in the respective device bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). Address inputs also provide the op-code
during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Data I/O: Data bus.
Not Connected: These pins should be left unconnected.
Do Not Use: These pins are not connected on these modules, but
are assigned pins on other modules in this product family.
4
64MB, 128MB, 256MB (x64, DR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
144-PIN SDRAM SODIMM
©2004 Micron Technology, Inc. All rights reserved.