mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 20

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
command must be asserted at least once every
140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB);
burst refreshing or posting by the DRAM control-
ler greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportionally with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 7, Derating Data Valid Window,
shows derating curves for duty cycles ranging
between 50/50 and 45/55.
result in a fail value. CKE is HIGH during RE-
FRESH command period (
LOW (i.e., during standby).
the input must:
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
50/50
3.750
2.500
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-26A/-265 @
-26A/-265 @
-335 @
t
HP (
2.463
t
CK = 6ns
t
Figure 7: Derating Data Valid Window
t
CK/2),
RFC [MIN]) else CKE is
49/51
3.650
t
t
CK = 10ns
CK = 7.5ns
2.425
t
DQSQ, and
48.5/52.5
3.600
2.388
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
(
3.550
48/52
t
t
QH
QH -
2.350
Clock Duty Cycle
20
t
DQSQ)
47.5/53.5
3.500
26. CK and CK# input slew rate must be
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30. HP min is the lesser of
2.313
ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncertain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM UDIMM
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
47/53
3.450
must not vary more than 4 percent if CKE is
2.275
IH
IH
(AC).
(DC).
46.5/54.5
3.400
2.238
3.350
46/54
2.200
©2004 Micron Technology, Inc. All rights reserved.
t
CL minimum and
45.5/55.5
3.300
2.163
3.250
45/55
1V/ns (2V/
2.125
t
DS and
IL
IL
(DC)
(AC)
t
CH