mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 4

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
115
44, 45, 49, 51, 134, 135, 142,
5, 14, 25, 36, 47, 56, 67, 78,
97, 107, 119, 129, 140, 149,
27, 29, 32, 37, 41, 43, 48,
125, 130, 141, 167
16, 17, 75, 76, 137, 138
(512MB,
PIN NUMBERS
159, 169, 177
63, 65, 154
157, 158
21, 111
52, 59
144
86
1GB), 118, 122,
Pin Descriptions
(2GB)
WE#, CAS#, RAS#
CK1#, CK2, CK2#
CK0, CK0#, CK1,
(512MB, 1GB)
DQS0–DQS8
CKE0, CKE1
DM0
SYMBOL
BA0, BA1
CB0–CB7
(256MB)
S0#, S1#
A0–A11
A0–A12
A0–A13
(2GB)
–
DM8
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V
brought HIGH. After CKE is brought HIGH, it becomes an
SSTL_2 input only.
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Check bits.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
DESCRIPTION
DD
is applied and until CKE is first
©2004 Micron Technology, Inc. All rights reserved.