mt9v032 aptina, mt9v032 Datasheet - Page 15

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Serial Bus Description
Protocol
Sequence
Bus Idle State
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Registers are written to and read from the MT9V032 through the two-wire serial inter-
face bus. The MT9V032 is a serial interface slave with four possible IDs (0x90, 0x98,
0xB0,and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is
transferred into the MT9V032 and out through the serial data (S
line is pulled up to V
pull the S
allowed to pull the S
can be accessed through 16- or 8-bit two-wire serial interface sequences.
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device 8-bit address
• a(n) (no) acknowledge bit
• an 8-bit message
• a stop bit
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device’s 8-bit address. The last bit of the address deter-
mines if the request is a read or a write, where a “0” indicates a write and a “1” indicates
a read. The slave device acknowledges its address by sending an acknowledge bit back to
the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data 8 bits at a time, with the
slave sending an acknowledge bit after each 8 bits. The MT9V032 uses 16-bit data for its
internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits
are transferred, the register address is automatically incremented, so that the next 16 bits
are written to the next register address. The master stops writing by sending a start or
stop bit.
A typical read sequence is executed as follows. First the master sends the write mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read mode slave address. The master then clocks out the register
data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The
register address is auto-incremented after every 16 bits is transferred. The data transfer
is stopped when the master sends a no-acknowledge bit. The MT9V032 allows for 8-bit
data transfers through the two-wire serial interface by writing (or reading) the most
significant 8 bits to the register and then writing (or reading) the least significant 8 bits to
R0xF0 (240).
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
DATA
line down—the serial interface protocol determines which device is
DD
DATA
off-chip by a 1.5KΩ resistor. Either the slave or master device can
line down at any given time. The registers are 16-bit wide, and
16
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
DATA
Serial Bus Description
) line. The S
DATA