mt9v032 aptina, mt9v032 Datasheet - Page 56

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

LINE_VALID
Figure 33:
LVDS Serial (Stand-Alone/Stereo) Output
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Different LINE_VALID Formats
By setting bit 2 and 3 of R0x74, the LINE_VALID signal can get three different output
formats. The formats for reading out four rows and two vertical blanking rows are shown
in Figure 33. In the last format, the LINE_VALID signal is the XOR between the contin-
uous LINE_VALID signal and the FRAME_VALID signal.
The LVDS interface allows for the streaming of sensor data serially to a standard off-the-
shelf deserializer up to five meters away from the sensor. The pixels (and controls) are
packeted—12-bit packets for stand-alone mode and 18-bit packets for stereoscopy
mode. All serial signalling (CLK and data) is LVDS. The LVDS serial output could either
be data from a single sensor (stand-alone) or stream-merged data from two sensors (self
and its stereoscopic slave pair). The appendices describe in detail the topologies for
both stand-alone and stereoscopic modes.
There are two standard deserializers that can be used. One for a stand-alone sensor
stream and the other from a stereoscopic stream. The deserializer attached to a stand-
alone sensor is able to reproduce the standard parallel output (8-bit pixel data,
LINE_VALID, FRAME_VALID and PIXCLK). The deserializer attached to a stereoscopic
sensor is able to reproduce 8-bit pixel data from each sensor (with embedded
LINE_VALID and FRAME_VALID) and pixel-clk. An additional (simple) piece of logic is
required to extract LINE_VALID and FRAME_VALID from the 8-bit pixel data. Irrespec-
tive of the mode (stereoscopy/stand-alone), LINE_VALID and FRAME_VALID are always
embedded in the pixel data.
In stereoscopic mode, the two sensors run in lock-step, implying all state machines are
in the same state at any given time. This is ensured by the sensor-pair getting their sys-
clks and sys-resets in the same instance. Configuration writes through the two-wire
serial interface are done in such a way that both sensors can get their configuration
updates at once. The inter-sensor serial link is designed in such a way that once the slave
PLL locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the
master sensor streams good stereo content irrespective of any variation voltage and/or
temperature as long as it is within specification. The configuration values of data-dly,
shft-clk-dly and stream-latency-sel are either predetermined from the board layout or
can be empirically determined by reading back the stereo-error flag. This flag gets
asserted when the two sensor streams are not in sync when merged. The combo_reg is
used for out-of-sync diagnosis.
FRAME_VALID
FRAME_VALID
FRAME_VALID
Continuously
LINE_VALID
LINE_VALID
LINE_VALID
Default
XOR
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MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
Feature Description