mt9v032 aptina, mt9v032 Datasheet - Page 30

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 8:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Bit
0x70 (112) Row Noise Correction Control 1
0x72 (114) Row Noise Constant
0x73 (115) Row Noise Correction Control 2
0x74 (116) Pixel Clock, FRAME and LINE VALID Control
3:0
7:0
9:0
11
4
5
0
1
2
3
4
Number of Dark
Pixels
Reserved
Enable noise
correction
Use black level
average
Row noise
constant
Dark start column
address
Invert Line Valid
Invert Frame Valid Invert frame valid. When set, FRAME_VALID is reset to
XOR Line Valid
Continuous Line
Valid
Invert Pixel Clock
Bit Name
Register Descriptions (continued)
The number of pixels used in the row-wise noise
calculation.
0 = 2 pixels.
1 = 4 pixels.
2 = 6 pixels.
4 = 10 pixels.
8 = 18 pixels.
See “Row-wise Noise Correction” on page 50 for
additional information.
Reserved.
0 = Normal operation.
1 = Enable row noise cancellation algorithm. When this
bit is set, on a per row basis, the dark average is
subtracted from each pixel in the row, and then a
constant (R0x72) is added.
1 = Use black level frame average from the dark rows in
the row noise correction algorithm for low gains. This
frame average was taken before the last adjustment of
the offset DAC for that frame, so it might be slightly off.
0 = Use the average value of the dark columns read out
in each row as dark average.
Constant used in the row noise cancellation algorithm.
It should be set to the dark level targeted by the black
level algorithm plus the noise expected between the
averaged values of dark columns. At default the
constant is set to 42 LSB.
The starting column address for the dark columns to be
used in the row-wise noise correction algorithm.
Invert line valid. When set, LINE_VALID is reset to logic
“0” when D
logic “0” when frame is valid.
1 = Line valid = "Continuous" Line Valid XOR Frame Valid
0 = Line Valid determined by bit 3. Ineffective if
Continuous Line Valid is set.
1 = "Continuous" Line Valid (continue producing line
valid during vertical blank).
0 = Normal Line Valid (default, no line valid during
vertical blank).
Invert pixel clock. When set, LINE_VALID, FRAME_VALID,
and D
PIXCLK. When clear, they are set up to the falling edge
of PIXCLK.
OUT
is set up to the rising edge of pixel clock,
OUT
is valid.
Bit Description
31
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Default in
Hex (Dec)
(759)
(42)
2F7
2A
4
1
1
0
0
0
0
0
0
Aptina reserves the right to change products or specifications without notice.
Shadowed
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
©2005 Aptina Imaging Corporation. All rights reserved.
0, 1, 2, 4, 8
759–775
Values
0–255
Legal
(Dec)
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
Registers
Read/
Write
W
W
W
W
W
W
W
W
W
W