mt9v032 aptina, mt9v032 Datasheet - Page 35

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 8:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Bit
0xBD (189) Maximum Total Shutter Width
0xBE (190) AGC/AEC Bin Difference Threshold
0xBF (191) Field Vertical Blank
0xC0 (192) Monitor Mode Capture Control
0xC1 (193) Thermal Information
0xC2 (194) Analog Controls
0xC3 (195) NTSC Frame Valid Control
0xC4 (196) NTSC Horizontal Blanking Control
0xC5 (197) NTSC Vertical Blanking Control
11:13 V_rst_lim voltage
15:0
15:8
15:8
7:0
8:0
7:0
9:0
7:0
7:0
6
7
0
1
Maximum Total
Shutter Width
Bin Difference
Threshold
Field Vertical
Blank
Image Capture
Numb
Temperature
Output
Reserved
Anti-Eclipse
Enable
Level
Extend Frame
Valid
Replace FV/LV
with Ped/Snyc
Front porch width The front porch width in number of master clock cycle.
Sync Width
Equalizing Pulse
Width
Vertical Serration
Width
Bit Name
Register Descriptions (continued)
This register is used by the automatic exposure control
(AEC) as the upper threshold of exposure. This ensures
the new calibrated integration value does not exceed
that which the MT9V032 supports.
This register is used by the AEC only when exposure
reaches its minimum value of 1. If the difference
between desired bin (R0xA5) and current bin (R0xBC) is
larger than the threshold, the exposure is increased.
The number of blank rows between odd and even fields.
Note: For interlaced (both field) mode only. See
R0x07[2:0].
The number of frames to be captured during the wake-
up period when monitor mode is enabled.
Status register to report the temperature of sensor.
Updated once per frame.
Reserved.
Setting this bit turns on anti-eclipse circuitry.
V_rst_lim = bits (2:0) × 50mV + 1.95V
Range: 1.95–2.30V; Default: 2.00V
Usage: For anti-eclipse reference voltage control
When set, frame valid is extended for half-line in length
at the odd field.
When set, frame valid and line valid is replaced by ped
and sync signals respectively.
NTSC standard is 1.5μsec ±0.1μsec
The sync pulse width in number of master clock cycle.
NTSC standard is 4.7μsec ±0.1μsec.
The pulse width in number of master clock cycle. NTSC
standard is 2.3μsec ±0.1μsec.
The pulse width in number of master clock cycle. NTSC
standard is 4.7μsec ±0.1μsec.
Bit Description
36
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Default in
Hex (Dec)
(480)
01E0
(20)
(22)
(10)
(22)
044
(68)
(33)
(68)
14
16
0A
16
21
44
1
0
1
0
0
Aptina reserves the right to change products or specifications without notice.
Shadowed
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
©2005 Aptina Imaging Corporation. All rights reserved.
1–2047
Values
0–255
0–255
0–255
0–255
0–255
0–255
Legal
(Dec)
0–63
0–7
0, 1
0, 1
0, 1
0, 1
Registers
Read/
Write
W
W
W
W
W
W
W
W
W
W
W
W
W
R