mt9v032 aptina, mt9v032 Datasheet - Page 16

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Start Bit
Stop Bit
Slave Address
Table 6:
Data Bit Transfer
Acknowledge Bit
No-Acknowledge Bit
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Slave Address Modes
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1
bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates
read mode. As indicated above, the MT9V032 allows four possible slave addresses deter-
mined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1.
One data bit is transferred during each clock pulse. The two-wire serial interface clock
pulse is provided by the master. The data must be stable during the HIGH period of the
serial clock—it can only change when the two-wire serial interface clock is LOW. Data is
transferred 8 bits at a time, followed by an acknowledge bit.
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
{S_CTRL_ADR1, S_CTRL_ADR0}
00
01
10
11
17
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Slave Address
0x90
0x91
0x98
0x99
0xB0
0xB1
0xB8
0xB9
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
Serial Bus Description
Write/Read Mode
Write
Write
Write
Write
Read
Read
Read
Read