mt9v032 aptina, mt9v032 Datasheet - Page 70

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Broadcast and Individual Writes for Stereoscopic Topology
Figure 48:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Two-Wire Serial Interface Configuration in Stereoscopic Mode
Note:
In stereoscopic mode, the two sensors are required to run in lockstep. This implies that
control logic in each sensor is in exactly the same state as its pair on every clock. To
ensure this, all inputs that affect control logic must be identical and arrive at the same
time at each sensor.
These inputs include:
• system clock
• system reset
• two-wire serial interface clk - SCL
• two-wire serial interface data - SDA
The setup in Figure 48 shows how the two sensors can maintain lockstep when their
configuration registers are written through the two-wire serial interface. A WRITE to
configuration registers would either be broadcast (simultaneous WRITES to both
sensors) or individual (WRITE to just one sensor at a time). READs from configuration
registers would be individual (READs from just one sensor at a time).
One of the two serial interface slave address bits of the sensor is hardwired. The other is
controlled by the host. This allows the host to perform either a broadcast or a one-to-
one access.
Broadcast WRITES are performed by setting the same S_CTRL_ADR input bit for both
slave and master sensor. Individual WRITES are performed by setting opposite
S_CTRL_ADR input bit for both slave and master sensor. Similarly, individual READs are
performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor.
26.6 MHz
The stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and
master sensor’s codes at this reserved byte must match). If the flag is set, steps 11 and
12 are repeated until the stereo_error_flag remains cleared.
Osc.
All system clock lengths (L) must be equal.
SCL and SDA lengths to each sensor (from the host) must also be equal.
HOST
L
CLK
SCL
SDA
L
S_CTRL_ADR[0]
SCL
71
SENSOR
SLAVE
Host launches SCL and SDA on positive
edge of SYSCLK.
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
L
SDA
CLK
S_CTRL_ADR[0]
Appendix A – Serial Configurations
SCL
Aptina reserves the right to change products or specifications without notice.
MASTER
SENSOR
©2005 Aptina Imaging Corporation. All rights reserved.
SDA
CLK