saa5250 NXP Semiconductors, saa5250 Datasheet - Page 10

• Manufacturer Part Number: saa5250
• Description: Interface For Data Acquisition And Control For Multi-standard Teletext Systems
• Manufacturer: NXP Semiconductors

Philips Semiconductors
R3 register
Table 7 R3 register contents
This 6-bit byte gives:
R4 register
Table 8 R4 register contents
R5 register
Table 9 R5 register contents
Note
1. F = data clock acquisition frequency (DCK).
Using R57 it is possible to start the internal synchronization delay (t
R6 write command register
This is a fictitious register. Only the address code (see Table 2) is required to reset the CIDAC. See Table 11 for the
status of the FIFO memory on receipt of this command.
R7 register
Table 10 R7 register contents
Note
1. F = data clock acquisition frequency.
January 1987
In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple errors on the
Hamming corrector)
A possible 63-bit format for all types of prefix
Interface for data acquisition and control
(for multi-standard teletext systems)
R47 TO R40
8-bit register used for storing the framing code value which will be compared with the third byte of each data
line
R57
NEGATIVE/POSITIVE
0 = negative edge for sync signal
1 = positive edge for sync signal
R75 TO R70
6-bit register used to give a maximum colour burst blanking signal of: (2
R35 TO R30
6-BIT FORMAT MAXIMUM/DEFAULT VALUE
000000 = 0
000001 = 1
111111 = 63
10
R56 TO R50
SYNCHRONIZATION DELAY
7-bit sync delay, giving a maximum
delay of (2
DVAL
) on the positive or negative edge.
7
1)
6
10
1) 10
6
s/F (Hz)
6
s/F (Hz)
Product specification
SAA5250