saa5250 NXP Semiconductors, saa5250 Datasheet - Page 11

• Manufacturer Part Number: saa5250
• Description: Interface For Data Acquisition And Control For Multi-standard Teletext Systems
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Fifo status register ( read R0 register)
Table 11 Fifo register contents
Once the relevant prefix and the right working modes have been given by the corresponding registers, a write command
to the R6 register enables the CIDAC to accept and process serial data.
Channel comparator
This is a four bit comparator which compares the three user hexadecimal defined values in R1 and R2 to corresponding
bytes of the prefix coming from the Hamming corrector. If the three bytes match, the internal process of the prefix
continues. If they do not match the CIDAC returns to a wait state until the next broadcast data package is received.
FIFO memory controller
The FIFO memory contains all the necessary functions required for the control of the 11-bit address memory (2 K byte).
The functions contained in the FIFO memory are as follows:
The FIFO memory provides the memory interface with the following:
January 1987
write address register (11-bits)
read address register (11-bits)
memory pointer (11-bits)
address multiplexer (11-bits)
write data register (8-bits)
read data register (8-bits)
data multiplexer
control logic
11-bit address bus (A10 to A0)
8-bit data bus (D7 to D0)
two control signals, memory select (MS) and write enable (WE)
Interface for data acquisition and control
(for multi-standard teletext systems)
DB2 TO DB0
DB2 = 1
memory empty
DB1 = 1, data not present in the
read data register
11
DB0 = 0
memory not full
Product specification
SAA5250