saa5250 NXP Semiconductors, saa5250 Datasheet - Page 12

• Manufacturer Part Number: saa5250
• Description: Interface For Data Acquisition And Control For Multi-standard Teletext Systems
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Operation
The CIDAC uses the same clock signal for data acquisition and internal processing, this allows the CIDAC to have a write
and a read cycle during each character period (see Fig.13). The first half of the character period is a write cycle and the
second half is a read cycle. Consequently, for an 8 MHz bit rate the maximum memory cycle time is 500 ns.
When the first data byte is written into the FIFO memory, thus transferred into the read register, the FIFO memory enters
the status shown in Table 12.
Table 12 FIFO status
When the FIFO memory is full two events occur:
Memory interface
The memory interface contains all the buffers for the memory signals mentioned in the section ‘FIFO memory controller’.
Page detection
This part of the CIDAC contains a parallel register with logic which detects (only in fast mode) a start of a page or data
group (see section ‘R0 register’).
Hamming correction (see Tables 13 and 14)
The Hamming correction provides (see section ‘Prefix processing’):
January 1987
the write address register points to the next address after the last written address
when new data is to be written, the memory select signal output ceases
hexadecimal value of the Hamming code
accept/reject code signal
parity information
Interface for data acquisition and control
(for multi-standard teletext systems)
DB2 TO DB0
DB2 = 1
memory empty
DB1 = 0
data available
12
DB0 = 0
memory not full
Product specification
SAA5250