ne564d NXP Semiconductors, ne564d Datasheet
ne564d
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ne564d Summary of contents
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... ANALOG OUT 4 13 FREQ. SET CAP 5 12 FREQ. SET CAP 6 11 VCO OUT GND VCO OUT TTL 8 9 TOP VIEW SR01025 Figure 1. Pin Configuration ORDER CODE DWG # NE564D SOT109-1 NE564N SOT38-4 SE564N SOT38-4 14 SCHMITT TRIGGER 16 15 SR01026 853-0908 13720 ...
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Philips Semiconductors Phase-locked loop ABSOLUTE MAXIMUM RATINGS SYMBOL V+ Supply voltage Pin 1 Pin 10 I Sink Max (Pin 9) and sourcing (Pin 11) OUT I Bias current adjust pin (sinking) BIAS P Power dissipation D Operating ambient temperature T ...
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Philips Semiconductors Phase-locked loop TYPICAL PERFORMANCE CHARACTERISTICS Lock Range vs Signal Input 1000 PIN 100 0.7 0.8 0.9 NORMALIZED LOCK RANGE Typical Noirmalized VCO Frequency as a Function of ...
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Philips Semiconductors Phase-locked loop TYPICAL PERFORMANCE CHARACTERISTICS (Continued) V – PHASE COMPARATOR’S D OUTPUT VOLTAGE IN mV 800 600 800 A BIAS 400 200 40 60 100 –200 –400 –600 –800 Variation of the Comparator’s Output Voltage ...
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Philips Semiconductors Phase-locked loop FUNCTIONAL DESCRIPTION (Figure 6) The NE564 is a monolithic phase-locked loop with a post detection processor. The use of Schottky clamped transistors and optimized device geometries extends the frequency of operation to greater than 50MHz. In ...
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Philips Semiconductors Phase-locked loop EQUIVALENT SCHEMATIC FM INPUT f = 5MHz 1kHz M BIAS FILTER 1994 Aug 31 Figure 6. Equivalent Schematic LOCK RANGE ADJUSTMENT I 2 0.01 F LOOP FILTER 0. ...
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Philips Semiconductors Phase-locked loop APPLICATIONS FM Demodulator The NE564 can be used demodulator. The connections for operation at 5V and 12V are shown in Figures 7 and 8, respectively. The input signal is AC coupled with the ...
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Philips Semiconductors Phase-locked loop 6. If pulsed burst or ramp frequency is used for input signal, special loop filter design may be required in place of simple single capacitor filter on Pins 4 and 5. (See PLL application section) 7. ...
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Philips Semiconductors Phase-locked loop Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs INPUT SIGNAL *NOTE: Use R only if rise time is critical. 9-11 Figure 12. NE564 Phase-Locked Frequency Multiplier 1994 Aug 31 +5V BIAS ...