ne564d NXP Semiconductors, ne564d Datasheet - Page 8

• Manufacturer Part Number: ne564d
• Description: Ne564 Phase-locked Loop
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6. If pulsed burst or ramp frequency is used for input signal, special
7. The input signal to Pin 6 and the VCO feedback signal to Pin 3
1994 Aug 31
Phase-locked loop
loop filter design may be required in place of simple single
capacitor filter on Pins 4 and 5. (See PLL application section)
must have a duty cycle of 50% for proper operation of the phase
detector. Due to the nature of a balanced mixer if signals are not
*NOTE:
Use R
9-11
only if rise time is critical.
INPUT
FSK
+5V
0.1 F
Figure 10. 10.8MHz FSK Decoder Using the 564
0.1 F
510
*510
+5V
2k
300pF
300pF
1k
1k
BIAS
ADJ
10k
11
2
6
7
3
9
4
5
1
10
0.22 F
HYSTERESIS
ADJUST
8
NE564
0.22 F
8. For multiplier circuits where phase jitter is a problem, loop filter
50% in duty cycle, DC offsets will occur in the loop which tend to
create an artificial or biased VCO.
capacitors may be increased to a value of 10 - 50 F on Pins 4,
5. Also, careful supply decoupling may be necessary. This
includes the counter chain V
15
10k
2k
16
1.2k
14
12
13
8
33pF
FSK
OUTPUT
10 F/8V
0–20pF
CC
lines.
NE/SE564
Product specification
SR01034