r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 45
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r8a66597
Manufacturer Part Number
r8a66597
Description
Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A66597.pdf
(185 pages)
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Part Number
Manufacturer
Quantity
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r8a66597BG
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Part Number:
r8a66597FP
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RENESAS/瑞萨
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Part Number:
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R8A66597FP/DFP/BG
Remarks
None
2.8.16 Buffer memory valid flag (BVAL)
R e v 1 . 0 1
11-0
♦ CFIFO port control register [CFIFOCTR]
♦ D0FIFO port control register [D0FIFOCTR]
♦ D1FIFO port control register [D1FIFOCTR]
Bit
15
14
13
12 Unassigned. Fix to "0".
BVAL BCLR FRDY
15
0
-
BVAL
Buffer memory valid flag
BCLR
CPU buffer clear
FRDY
FIFO port ready
DTLN
Reception data length
When the pipe specified in the CURPIPE bit is transmitting, write "1" to this bit in the cases below. The controller writes
the FIFO buffer from the CPU side to the SIE side to make transmission possible.
(1) To transmit the short packet, write "1" to this bit after the data is written.
(2) To transmit a zero-Length packet, write "1" to this bit before writing the data to FIFO.
(3) For the pipe in continuous transfer mode, write "1" to this bit after writing the maximum packet size in multiples of
If the data of the maximum packet size is written for the pipe in continuous transfer mode, the controller writes "1" to
this bit, sets the CPU FIFO buffer to the SIE side, and changes to transmission possible status.
When the controller indicates "FRDY=1", write "1" to this bit.
When the specified pipe is receiving, do not write "1" to this bit.
14
0
-
natural integers and data less than the buffer size.
O c t 1 7 , 2 0 0 8
Name
13
0
-
12
?
?
p a g e 4 5 o f 1 8 3
Specify "1" when write of the FIFO buffer ends on the CPU
side of pipe specified in CURPIPE.
0: Invalid
1: Writing ended
Specify "1" to clear the FIFO buffer on the CPU side of the
pipe.
0: Invalid
1: Clears the CPU buffer memory
Indicates whether the FIFO port can be accessed.
0: FIFO port access disabled
1: FIFO port access enabled
Displays reception data length of FIFO buffer for
corresponding PIPE.
11
0
-
10
0
-
9
0
-
8
0
-
Function
7
0
-
6
0
-
DTLN
5
0
-
4
0
-
R(0)/W(1)
Software Hardware Remarks
R/W(1)
3
0
-
R
R
2
0
-
R/W(0)
R/W
W
W
<Address: 2AH>
<Address: 2EH>
<Address: 22H>
1
0
-
0
0
-