hi-6110 Holt Integrated Circuits, Inc., hi-6110 Datasheet

hi-6110

Manufacturer Part Number

hi-6110

Description

Bc / Rt / Mt Message Processor

Manufacturer

Holt Integrated Circuits, Inc.

Datasheet

1.HI-6110.pdf (37 pages)

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GENERAL DESCRIPTION

The HI-6110 is a CMOS integrated circuit implementing the

MIL-STD-1553 (1553) data communications protocol

between a host processor and a dual redundant 1553 data

bus. The single chip architecture has a digital section

containing all necessary logic and memory to process and

store the command and data words for one complete 1553

message. The analog section includes dual transceivers

coupled to the 1553 buses through external current mode

transformers. The device is available in an industry standard

64-pin 9 mm square QFN package, making it the smallest

dual redundant 1553 interface product on the market.

The HI-6110 may be configured as a Bus Controller (BC), a

Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor

Terminal with assigned RT address. 16-bit registers store

incoming and outgoing Command, Status and Data words.

Using two 32-word data FIFOs, the HI-6110 can store the

maximum number of 1553 words occurring in any message.

For messages with transmitted data words, data may be

written in advance or on-the-fly. Received data can be

retrieved on-the-fly or all at once after the Valid Message flag

is asserted.

BC message sequences are initiated by a rising edge on the

BCSTART input, or a 0 to 1 transition at the BCSTART bit in

the Control Register.

automatically initiated after a valid Command Word is

received.

A single encoder services both buses, each of which have a

dedicated analog transformer driver. Each driver dissipates

less than 200 mW of on-chip power at 100% duty cycle.

Each bus receiver has a dedicated Manchester decoder. In

BC mode, a RCV signal indicates when valid 1553 words are

received. In RT/MT modes, RCV indicates a valid command

received, while the 1553 command decoder updates a

Message register so the external controller can identify

command type and respond appropriately. Guaranteed by

design, the HI-6110 cannot generate messages exceeding

660uS, the duration of a Command or Status Word plus 32

contiguous data words.

The external host controller reads and writes a simplified

The system designer has flexibility over many aspects of

configuration. Control and status monitoring can be done in

hardware (by reading/writing control pins) or in software (by

reading/writing register bits).

(DS6110 Rev. L)

(

May 2008

All RT command responses are

HOLT INTEGRATED CIRCUITS

www.holtic.com

BC / RT / MT Message Processor

PIN CONFIGURATION

FEATURES

APPLICATIONS

MIL-STD-1553 / MIL-STD-1760

D10 - 13

•

D0 - 3

D1 - 4

D2 - 5

D3 - 6

D4 - 7

D5 - 8

D6 - 9

D7 - 10

D9 - 12

D8 - 11

• Monolithic CMOS Technology

• 3.3V operation

• Exceptionally low power

• On-chip message buffering

• Selectable master clock frequency

• Dual differential 1553 bus transceivers

• Bus Controller / Remote Terminal /

• Compliant to MIL-STD-1553B Notice 2

Test Equipment

MIL-STD-1553 Terminals

Flight Control and Monitoring

ECCM Interfaces

Stores Management

Sensor Interfaces

Instrumentation

- 1

- 2

Monitor Terminal operating modes

and MIL-STD-1760 Stores Management

52 Pin Plastic Quad Flat Pack (PQFP)

See page 35 for 64-Pin QFN Pin Configuration

HI-6110PQT

HI-6110PQI

HI-6110

(Top View)

39 - VDDA

38 -

37 - BUSB

36 - VDDB

35 -

34 - TXINHB

33 - RCVB

32 - FFEMPTY

31 - RF0 / RCMDA

30 - RF1 / RCMDB

29 -

28 - VALMESS

27 - ERROR

BUSA

BUSB

RFLAG

05/08

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