hi-6110 Holt Integrated Circuits, Inc., hi-6110 Datasheet - Page 15

• Manufacturer Part Number: hi-6110
• Description: Bc / Rt / Mt Message Processor
• Manufacturer: Holt Integrated Circuits, Inc.

MSB
MSB
STATUS REGISTER (Read only) Read Address: 0101
BIT
15- 9
8
7
6
5
4
3
2
1
0
BIT
15 - 10
9
8
7
6
5
4
3
2
1
0
ERROR REGISTER (Read only) Read Address: 0111
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
0
0
0
NAME
-
ERROR
VALMESS
RF1
RF0
RFLAGN
FFEMPTY
RCVB
RCVA
IDLE
NAME
-
RTPARERR
-
FFERR
-
CONERR
GAPERR
SEQERR
SYNCERR
MANERR
NORCV
Not used
Not used
0
Not used
0
0
0
0
0
0
0
0
FUNCTION
Not used. These bits are set to "0".
This bit is reset to "0" after MR, and will automatically reset 2 to 3 uS after assertion if Control register RERR
bit is set. ERROR is set to a "1" if the last sequence had an error. The nature of the message error can be
determined by examining the Error Register. The ERROR output pin reflects the state of this bit.
This bit is a "0" after reset or after a MIL-STD-1553 message containing an error. VALMESS goes high
upon completion of an error-free MIL-STD-1553 message sequence. VALMESS is reset to a zero each
time a valid command is received on the active bus. The VALMESS output pin mirrors the state of
this bit.
This bit goes high when a valid Receive Command arrives on Bus B. It is reset by the RCV B flag.
This bit goes high when a valid Receive Command arrives on Bus A. It is reset by the RCV A flag.
During a message sequence this bit goes low at the arrival of a Command Word, Status Word, or Mode
Data Word. For consecutive words, this bit will momentarily go high between words. The
reflects the state of this bit.
If "0", the receive Data FIFO contains at least one unread data word. This bit is set to "1" upon master reset,
or when the user has read all available received data words from the receiver Data FIFO. The FFEMPTY
output pin reflects the state of this bit.
Set to "1" upon receipt of a valid Command Word on Bus B except for RT-to-RT receive commands when it
is set after the second Command Word is received. The RCVB output pin mirrors the state of this bit.
Set to "1" upon receipt of a valid Command Word on Bus A
is set after the second Command Word is received The RCV output pin mirrors the state of this bit.
If "1", the RT is idle. This bit is “0” throughout the time the RT is processing a valid MIL-STD-1553
Command message. The bit returns to a "1" when the message is completed.
FUNCTION
Not used. These bits are set to "0".
RT Parity Error in the pin-programmed RT address. RT address parity is checked only at Master Reset, and
once this bit is set, the host controller must perform a subsequent Master Reset to update parity status.
Data was not available in the Transmit Data FIFO.
Not used.
Contiguous Message Error: Transmission was not contiguous.
Bus activity was detected in the 4.0 uS gap after a valid message was completed.
The next event after a Command Word was erroneous. For example, a gap following a valid receive
Command Word, or a contiguous Data Word following a transmit Command Word.
Sync Error: Expected Command Sync and got Data Sync, or vice versa.
Manchester Encoding Error: The decoder detected an error in Manchester encoding, bit count or parity.
This bit is set when a data word is expected while processing a receive command, but a gap is detected.
It is also set when an RT-to-RT "No Response Timeout" occurs, as defined per MIL-HDBK-1553, Figure 8
"RT-RT Timeout Measurement". The HI-6110 asserts this error when the bus dead-time between the RT-
RT command pair and the transmit RT Status Word exceeds 15 uS.
Not used. This bit is set to "0".
8
0
8
7
7
HI-6110 (REMOTE TERMINAL MODE)
6
This bit is set to "0".
0
6
5
5
4
4
HOLT INTEGRATED CIRCUITS
3
3
2
2
1
RT OPERATION
1
0
0
LSB
LSB
15
The Status Register may be interrogated by the host at any
time. It provides information that allows the user to determine
whether the HI-6110 is busy executing a MIL-STD-1553
message and its progress. After a message sequence has
completed, the Status register indicates whether an error was
detected or if the message sequence was successful.
The RT Error Register is cleared at Master Reset and error
flags are automatically reset if Control Register bit 6 = “1”. If
an error is encountered during message execution, the
ERROR pin goes high, the ERROR bit is set in the Status
Register, and one or more bits are set in the Error Register to
specify the type of error detected.
.
except for RT-toRT receive commands when it
A
RFLAG
output