m28f410 STMicroelectronics, m28f410 Datasheet - Page 5

• Manufacturer Part Number: m28f410
• Description: 4 Megabit X8 Or X16, Block Erase Flash Memory
• Manufacturer: STMicroelectronics

Table 7. Status Register
Notes: Logic level ’1’ is High, ’0’ is Low.
is first applied, on exit from power down or if V
falls below V
Read Memory Array.
Instructions and Commands
Eight Instructions are defined to perform Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, Erase, Program, Clear Status
Register, Erase Suspend and Erase Resume. An
internalProgram/EraseController (P/E.C.) handles
all timing and verification of the Program and Erase
instructions and provides status bits to indicate its
operation and exit status. Instructions are com-
posed of a first command write operation followed
by either second command write, to confirm the
commands for programming or erase, or a read
operationto read data from the array, the Electronic
Signature or the Status Register.
For added data protection, the instructions for byte
or word program and block erase consist of two
commands that are written to the memory and
P/ECS
monic
VPPS
Mne-
ESS
ES
PS
LKO
Bit
7
6
5
4
3
2
1
0
, the command interface is reset to
P/E.C. Status
Erase
Suspend
Status
Erase Status
Program
Status
V
Reserved
Reserved
Reserved
PP
Name
Status
Level
Logic
’1’
’0’
’1’
’0’
’1’
’0’
’1’
’0’
’1’
’0’
Ready
Busy
Suspended
In progress or
Completed
Erase Error
Erase Success
Program Error
Program
Success
V
V
PP
PP
Definition
Low, Abort
OK
CC
be suspended in order to read data from another
block and then resumed. A Status Register may be
read at any time, including during the programming
or erase cycles, to monitor the progress of the
operation.
Power Saving
The M28F410 and M28F420 have a number of
power saving features. A CMOS standby mode is
entered when the Chip Enable E and the Re-
set/Power Down (RP) signals are at V
supply current drops to typically 60µA. A deep
power down mode is enabled when the Re-
set/Power Down (RP) signal is at V
supply current drops to typically 0.2µA. The time
required to awake from the deep power down mode
is 300ns maximum, with instructions to the C.I.
recognised after only 210ns.
which start the automatic P/E.C. operation. Byte or
word programming takes typically 9µs, block erase
typically 1 second. Erasure of a memory block may
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
PS bit set to ’1’ if the P/E.C. has failed to program
a byte or word.
VPPS bit is set if the V
V
has been executed.
PPH
(min) when a Program or Erase instruction
PP
Note
voltage is below
SS
CC
, when the
, when the
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