tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 14

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
Advance Data Sheet, Rev. 2
SONET/SDH x84/x63 Ultramapper
July 2001
2 The SONET/SDH Ultramapper
(continued)
2.3.2 Transmit Direction
In the transmit direction, the Ultramapper performs transmit transport overhead access channel (TTOAC) insertion,
synchronizing status byte (S1) insertion, M0/M1 — REI-L insertion, K1 and K2 insertion, AIS-L insertion, B2 calcula-
tion and insertion, F1 byte insertion, B1 generation and error insertion, scrambler, J0 insert control, and A2 error
insertion. All insert control functions that are inhibited will optionally insert either all zeros or all ones. The TTOAC
allows the users to insert the following overhead bytes: E1, F1, D1 : D3, D4 : D12, S1, and E2. Even or odd parity is
checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros stuff value. The
Ultramapper sources a clock and an 8 kHz synchronizing pulse and receives the data at a data rate of
5.184 Mbits/s. Alternatively, only the data communication channels D1 — D3 or D4 — D12 may receive a serial
192 kbits/s or a 576 kbits/s data stream.
The insertion (overwrite of TTOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled.
Automatic insertion of M0/M1 may be inhibited. A protection switch selects the REI-L value for insertion to be taken
from the protection board rather than from the receive side.
The entire APS value or K2[2:0] can be inserted via microprocessor control. Automatic RDI insertion is supported
with individual inhibit for each contributor. A protection switch selects the RDI-L value for insertion to be taken from
the protection board rather than from the receive side.
B1 and B2 BIP-8 values are calculated and inserted. Both values can be inverted.
2.4 Multiplex Section Protection (MSP 1 + 1)
The TMUX block supports a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer
interpretation. If the protection switch is activated, then the data is selected from the receive protection interface
rather than from the high-speed input path.
In the transmit direction, the signal is broadcast to the high-speed output path and the protection interface.
The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and synchronizing pulse in each direction.
2.4.1 Pointer Interpreter
This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996—
Annex B.
The pointer interpreter evaluates the current pointer state for the normal state, path AIS state, or LOP (loss of
pointer) conditions, as well as pointer increments and decrements. The current pointer state and any changes in
pointer condition are reported to the control system. The number of consecutive frames for invalid pointer and
invalid concatenation indication is fixed at nine.
2.4.2 Path Termination Function
The path termination function is performed on either all three STS-1s or on the VC-4 POH only.
It includes on the receive side: J1 monitoring, B3 BIP-8 checking, C2 signal label monitoring, REI-P and RDI-P
detection, H4 multiframe monitoring; F2, F3, and K3 automatic protection switch monitoring, N1 tandem connection
monitoring, signal degrade BER and signal fail BER detection; path overhead access channel (RPOAC) drop,
AIS-P/HO-AIS insertion, and automatic AIS generation (with individual inhibit).
The J1 monitor provides five modes of operation on a programmable length (1 byte — 64 bytes) of the trace identi-
fier: cyclic checking against the last received sequence, comparing against a programmed sequence, SONET
framing mode, SDH framing mode, and consecutive consistent occurrences of a new pattern.
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Agere Systems Inc.